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Bus based parallel computers: A viable way for massive parallelism

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 817))

Abstract

In most distributed memory MIMD multiprocessors, processors are connected by a point-to-point interconnection network. Since interprocessor communication frequently constitutes serious bottlenecks, several architectures were proposed that enhance point-to-point topologies with the help of multiple bus systems so as to improve the communication efficiency. In this paper we study global communication on parallel architectures where the communication means are constituted solely by busses. We focus on the hyperpath and the hypergrid architectures, which are the bus-based versions of the well used point-to-point linear and grid interconnection networks. Using (hyper) graph theoretic concepts in order to model inter-processor communication in such networks, we developed a new tool called simplification in order to give extremely efficient algorithms for gossiping (all-to-all or total exchange communications).

Partially supported by the PRC C 3 and ANM of the French CNRS.

Supported by FAPESP — Proc. No. 92/3991-0

Supported by FAPESP — Proc. No. 93/0603-1 and CNPq — Proc. No. 306063/88-3 and PROTEM-CC/SP.

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Costas Halatsis Dimitrios Maritsas George Philokyprou Sergios Theodoridis

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© 1994 Springer-Verlag Berlin Heidelberg

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Ferreira, A., vel Lejbman, A.G., Song, S.W. (1994). Bus based parallel computers: A viable way for massive parallelism. In: Halatsis, C., Maritsas, D., Philokyprou, G., Theodoridis, S. (eds) PARLE'94 Parallel Architectures and Languages Europe. PARLE 1994. Lecture Notes in Computer Science, vol 817. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58184-7_130

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  • DOI: https://doi.org/10.1007/3-540-58184-7_130

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-58184-0

  • Online ISBN: 978-3-540-48477-6

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