Abstract
The current trend is integrating more hardware functional units within the superscalar processor. However, the functional units are not fully utilized due to the inherent limit of instruction-level parallelism in a single instruction stream. The use of simultaneous execution of instructions from multiple streams, referred to as multistreaming, can increase the number of instructions dispatched per cycle by providing more ready-to-issue instructions. We present an analytical modeling technique to evaluate the effect of dynamically interleaving additional instruction streams within superscalar architectures. Estimates of the instructions executed per cycle (IPC) are calculated given simple descriptions of the workload and hardware. To validate this technique, estimates obtained from the model for several benchmarks are compared against results from a hardware simulator.
This research was supported by the State of California and Apple Computer Inc. via MICRO grant #92-178.
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© 1994 Springer-Verlag Berlin Heidelberg
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Serrano, M.J., Yamamoto, W., Wood, R.C., Nemirovsky, M. (1994). A model for performance estimation in a multistreamed superscalar processor. In: Haring, G., Kotsis, G. (eds) Computer Performance Evaluation Modelling Techniques and Tools. TOOLS 1994. Lecture Notes in Computer Science, vol 794. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58021-2_12
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DOI: https://doi.org/10.1007/3-540-58021-2_12
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