Skip to main content

A model for performance estimation in a multistreamed superscalar processor

  • Full Papers
  • Conference paper
  • First Online:

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 794))

Abstract

The current trend is integrating more hardware functional units within the superscalar processor. However, the functional units are not fully utilized due to the inherent limit of instruction-level parallelism in a single instruction stream. The use of simultaneous execution of instructions from multiple streams, referred to as multistreaming, can increase the number of instructions dispatched per cycle by providing more ready-to-issue instructions. We present an analytical modeling technique to evaluate the effect of dynamically interleaving additional instruction streams within superscalar architectures. Estimates of the instructions executed per cycle (IPC) are calculated given simple descriptions of the workload and hardware. To validate this technique, estimates obtained from the model for several benchmarks are compared against results from a hardware simulator.

This research was supported by the State of California and Apple Computer Inc. via MICRO grant #92-178.

This is a preview of subscription content, log in via an institution.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. A. Agarwal, B. Lim, D. Kranz, and Kubiatowicz, “APRIL: A Processor Architecture for Multiprocessing,” Proc. of the 17th Symposium on Computer Architecture, May 1990, pp. 104–114.

    Google Scholar 

  2. T. M. Conte, “Systematic Computer Architecture Prototyping,” Ph.D Thesis, Electrical Engineering, University of Illinois at Urbana-Champaign, 1992.

    Google Scholar 

  3. P. J. Courtois, Decomposability. Queuing and Computer System Applications. Academic Press. 1977.

    Google Scholar 

  4. S. I. Feldman, D. M. Gay, M. W. Maimone, and N.L. Schryer, “A Fortran-to-C Converter,” Computing Science Technical Report No. 149, AT&T Bell Laboratories, Murray Hill, NJ, 1991.

    Google Scholar 

  5. G. F. Grohoski, “Machine Organization of the IBM RISC System/6000 processor”, IBM Journal of Research and Development, Vol. 34, No. 1, January 1990, pp. 37–58.

    Google Scholar 

  6. J. L. Hennessy, and D. A. Patterson, Computer Architecture, A Quantitative Approach, Morgan Kaufmann Publishers, 1990.

    Google Scholar 

  7. W. J. Kaminsky, and E. S. Davidson, “Developing a Multiple-Instruction-Stream Single-Chip Processor,” IEEE Computer Magazine, Dec. 1979.

    Google Scholar 

  8. J. S. Kowalik, ed., Parallel MIMD Computation: HEP Supercomputer and its Applications, MIT Press, 1985.

    Google Scholar 

  9. M. D. Nemirovsky, F. Brewer, and R. C. Wood, “DISC: Dynamic Instruction Stream Computer,” Proceedings of the 24th ACM/IEEE International Symposium and Workshop on Microarchitecture, Albuquerque, NM, Nov. 1991, pp. 163–171.

    Google Scholar 

  10. M. Serrano, M. D. Nemirovsky, and R. C. Wood, “A Study on Multistreamed Superscalar Processors,” Technical Report #93-05, Department of Electrical and Computer Engineering, University of California, Santa Barbara, March 1993.

    Google Scholar 

  11. E. de Souza e Silva, P. M. Ochoa, “State Space Exploration in Markov Models”, Performance Evaluation Review, Vol. 20, No. 1, June 1992.

    Google Scholar 

  12. C. A. Staley, “Design and Analysis of the CCMP: A Highly Expandable Shared Memory Parallel Computer,” Ph.D Dissertation, University of California, Santa Barbara, August 1986.

    Google Scholar 

  13. B. Smith, R. Alverson, D. Callahan, D. Cummings, B. Koblenz, A. Porterfield. “The Tera Computer System”. Proceedings of Supercomputing'90. pp. 1–6.

    Google Scholar 

  14. K. B. Theobald, G. R. Gao, and L. J. Hendren, “On the Limits of Program Parallelism and its Smoothability“. IEEE Micro 25, Oct. 1992. pp. 10–19.

    Google Scholar 

  15. J. E. Thornton, “Parallel Operation in the Control Data 6600,” Proceedings Spring Joint Computer Conference, 1964.

    Google Scholar 

  16. E. H. Welbon, C.C. Chan-Nui, D.J. Shippy, and D.A. Hicks, “The Power2 Performance Monitor”, IBM RISC System/6000 Technology: Volume II. Sept. 23, 1993.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Günter Haring Gabriele Kotsis

Rights and permissions

Reprints and permissions

Copyright information

© 1994 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Serrano, M.J., Yamamoto, W., Wood, R.C., Nemirovsky, M. (1994). A model for performance estimation in a multistreamed superscalar processor. In: Haring, G., Kotsis, G. (eds) Computer Performance Evaluation Modelling Techniques and Tools. TOOLS 1994. Lecture Notes in Computer Science, vol 794. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58021-2_12

Download citation

  • DOI: https://doi.org/10.1007/3-540-58021-2_12

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-58021-8

  • Online ISBN: 978-3-540-48416-5

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics