Abstract
This paper shows several optimisations to the Hestenes parallel algorithm for Singular Value Decomposition (SVD). The central principle in all of the optimisations presented herein is to increase the number of columns being held in each level of the parallel memory hierarchy. The algorithm was implemented on the Fujitsu's AP1000 Array Multiprocessor, but all optimisations described can be easily applied to any MIMD architecture with mesh or hypercube topology, and all but one can be applied to register-cache uniprocessors also.
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References
Brent, R.P., Luk, F.T.: The Solution of Singular-Value and Symmetric Eigenvalue Problems on Multiprocessor Arrays SIAM Journal of Scientific and Statistical Computing 6 (1986) 69–84
Czezowski, A., Strazdins, P.: Ways of enhancing performance of a Singular Value Decomposition Algorithm on the AP1000 Array Multiprocessor. Transputer and Occam Engineering Series 31 (1993) 83–88 (ISSN:0925-4986)
Czezowski, A., Strazdins, P.: Optimisations for the memory hierarchy of a Singular Value Decomposition Algorithm implemented on the MIMD Architecture. ANU, Department of Computer Science Technical Report TR-CS-94-03 (1994)
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© 1994 Springer-Verlag Berlin Heidelberg
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Czezowski, A., Strazdins, P. (1994). Optimisations for the memory hierarchy of a Singular Value Decomposition algorithm implemented on the MIMD architecture. In: Gentzsch, W., Harms, U. (eds) High-Performance Computing and Networking. HPCN-Europe 1994. Lecture Notes in Computer Science, vol 797. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-57981-8_119
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DOI: https://doi.org/10.1007/3-540-57981-8_119
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