Advertisement

On computing power

  • Jean E. Vuillemin
Session Papers
Part of the Lecture Notes in Computer Science book series (LNCS, volume 782)

Abstract

We analyze in details some implementations of a challenging, yet simple application: CERN’s calorimeter. We try both general purpose computer architectures (single and multi processors, Simd and Mimd), and special purpose electronics (full-custom, gate-array, FPGA) on the problem.

All measures are expressed in a single common unit for computing power: the Gbops. It applies to all forms of digital processors, and across technologies. What's more, Noyce's thesis provides a reliable way to extrapolate Gbops benchmarks through future time, say up to year 2001.

The quantitative result of our analysis shows that special purpose processing is an order of magnitude more efficient than general purpose processing, on our specific problem. We show how to map the calorimeter on a programmable active memory PAM, at performance and cost comparable to those of fully dedicated implementations: orders of magnitude better than any general purpose implementation, in 1992. We argue that this current computational power advantage for PAM technology will increase with time.

Finally, we discuss how to program such novel virtual PAM computers in the 2Z language, for very large synchronous designs.

Keywords

Computing Power Digital Equipment Corporation Multi Processor Virtual Power 2adic Number 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    J. Arnold, D. Buell andE. Davis, Splash II, in 4th ACM Symposium on Parallel Algorithms and Architectures, San Diego, California, USA (1992).Google Scholar
  2. [2]
    Algotronix Ltd., The Configurable Logic Data Book, Edinburgh, UK (1990).Google Scholar
  3. [3]
    J. Badier, R. Bock et al., Evaluating Parallel Architectures for two Real-Time Applications with 100kHz repetition rate, EAST note, CERN.Google Scholar
  4. [4]
    P. Bertin, Mémoires actives programmables: conception, réalisation et programmation, Thèse, Université Paris 7,1993.Google Scholar
  5. [5]
    P. Bertin, D. Roncin, and J. Vuillemin, Introduction to Programmable Active Memories, in Systolic Array Processors, J. McCanny, J. McWhirter, E. Swartzlander Jr. editors, pp 301–309, Prentice-Hall (1989). Also as PRL report 3, Digital Equipment Corporation, Paris Research Laboratory, 85, av. Victor-Hugo, 92563 Rueil-Malmaison Cedex, France (1989).Google Scholar
  6. [6]
    P. Bertin, D. Roncin, and J. Vuillemin, Programmable Active Memories: a Performance Assessment, in Symposium on Integrated Systems, Seattle, WA, USA, March 1993, MIT Press (1993). Also as PRL report 24, Digital Equipment Corporation, Paris Research Laboratory, 85, av. Victor-Hugo, 92563 Rueil-Malmaison Cedex, France (1993).Google Scholar
  7. [7]
    P. Boucard, J. Vuillemin, and M. Shand, Calorimeter Collision Detector on DECPeRLe 1, PRL report 40, Digital Equipment Corporation, Paris Research Laboratory, 85, av. Victor-Hugo, 92563 Rueil-Malmaison Cedex, France (1994).Google Scholar
  8. [8]
    F. Bourdoncle, J. Vuillemin, and G. Berry, The 2Z Report, PRL report 36, Digital Equipment Corporation, Paris Research Laboratory, 85, av. Victor-Hugo, 92563 Rueil-Malmaison Cedex, France (1994).Google Scholar
  9. [9]
    W. S. Carter, K. Duong, R. H. Freeman, H. C. Hsieh, J. Y. Ja, J. E. Mahoney, L. T. Ngo, and S. L. Sze, A User Programmable Reconfigurable Logic Array, in Proc. IEEE 1986 Custom Integrated Circuits Conference, 233–235 (1986).Google Scholar
  10. [10]
    Concurrent Logic, Inc., Cli6000 Series Field-Programmable Gate Arrays, Concurrent Logic Inc., 1270 Oakmead Parkway, Sunnyvale, CA94086, USA (1992).Google Scholar
  11. [11]
    B. Heeb and C. Pfister, Chameleon, a Workstation of a Different Colour, in 2nd International workshop on Field-Programmable Logic and Applications, paper 5.6, Vienna, Austria (1992).Google Scholar
  12. [12]
    T.A. Kean and J.P. Gray, Configurable Hardware: two Case Studies of Micro-Grain Computation, in Systolic Array Processors, J. McCanny, J. McWhirter, E. Swartzlander Jr. editors, pp. 310–319, Prentice-Hall (1989).Google Scholar
  13. [13]
    Quickturn Systems, Inc., RPM Emulation System Data Sheet, Quickturn Systems, Inc., 325 East Middlefleld Road, Mountain View, CA 94043, USA (1991).Google Scholar
  14. [14]
    C. P. Thacker, Computing in 2001, Digital Equipment Corporation, Systems Research Center, 130 Lytton, Palo Alto, CA94301, U.S.A.Google Scholar
  15. [15]
    J. Vuillemin, A Combinatorial Limit to the Computing Power of VLSI Circuits, IEEE trans. on Computers, Avril 1983.Google Scholar
  16. [16]
    J. Vuillemin, On Circuits and Numbers, PRL report 25, Digital Equipment Corporation, Paris Research Laboratory, 85, av. Victor-Hugo, 92563 Rueil-Malmaison Cedex, France (1993).Google Scholar
  17. [17]
    Xilinx, Inc., The Programmable Gate Array Data Book, Xilinx, 2100 Logic Drive, San Jose, CA 95124, USA (1991).Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1994

Authors and Affiliations

  • Jean E. Vuillemin
    • 1
  1. 1.Paris Research LaboratoryDigital Equipment CorporationRueil Malmaison, CedexFrance

Personalised recommendations