FPGA based logic synthesis of squarers using VHDL

Abstract

In this paper, the design of VHDL coded squarers by using logic synthesis is considered. The square function is important for the digital processing of signals using e.g. matched filters and Viterbi equalizers in receivers for communication systems. However, many arithmetical functions like the square function are not supported by VHDL. Hence, two major drawbacks arise in the logic synthesis of VHDL code. Firstly, the designers are forced to implement the needed arithmetical functions in VHDL by themselves. Secondly, when implementing arithmetical functions such as the square function in VHDL, special care must by taken in order to circumvent massive hardware overhead of the synthesis results compared with manually designed architectures. In the case of the square function, this massive hardware overhead mainly stems from the fact that the synthesis results of squarers are as hardware expensive as the synthesis results of multipliers. In the course of the present paper, the authors shall demonstrate how this hardware overhead of squarers can be reduced by using a modified square algorithm (MSA) which was developed by the authors. The MSA was derived based on the Dadda algorithm which will be discussed briefly.