Abstract
This paper is an approach to automated verification of circuits represented as switch-level designs. Switch-level models (SLM) are a well-established framework for modelling low-level properties of circuits. We use many-valued prepositional logic to represent a suitable variant of SLM. Logical properties of circuits (gate-level) can be expressed in a standard way in the same logic. As a result we can express soundness of switch-level designs wrt to gate-level specifications as many-valued deduction problems. Recent advances in many-valued theorem proving indicate that it is possible to handle real life examples. We report first results obtained with an experimental theorem prover.
Research supported by IBM Germany and Deutsche Forschungsgemeinschaft.
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© 1993 Springer-Verlag Berlin Heidelberg
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Hähnle, R., Kernig, W. (1993). Verification of Switch-level designs with many-valued logic. In: Voronkov, A. (eds) Logic Programming and Automated Reasoning. LPAR 1993. Lecture Notes in Computer Science, vol 698. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-56944-8_50
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DOI: https://doi.org/10.1007/3-540-56944-8_50
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