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International Conference on Parallel Architectures and Languages Europe

PARLE 1993: PARLE '93 Parallel Architectures and Languages Europe pp 329–340Cite as

Locality and false sharing in coherent-cache parallel graph reduction

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 694))

Abstract

Parallel graph reduction is a model for parallel program execution in which shared-memory is used under a strict access regime with single assignment and blocking reads. We outline the design of an efficient and accurate multiprocessor simulation scheme and the results of a simulation study of the performance of a suite of benchmark programs operating under a cache coherency protocol that is representative of protocols used in commercial shared-memory machines and in more scalable distributed shared-memory systems. We analyse the influence of cache line size on performance and expose the relative contributions of spatial, temporal and processor locality and false sharing to overall performance.

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Authors and Affiliations

  1. Department of Computing, Imperial College of Science, Technology and Medicine, SW7 2BZ, London

    Andrew J. Bennett & Paul H. J. Kelly

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  1. Andrew J. Bennett
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  2. Paul H. J. Kelly
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Arndt Bode Mike Reeve Gottfried Wolf

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© 1993 Springer-Verlag Berlin Heidelberg

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Bennett, A.J., Kelly, P.H.J. (1993). Locality and false sharing in coherent-cache parallel graph reduction. In: Bode, A., Reeve, M., Wolf, G. (eds) PARLE '93 Parallel Architectures and Languages Europe. PARLE 1993. Lecture Notes in Computer Science, vol 694. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-56891-3_26

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  • DOI: https://doi.org/10.1007/3-540-56891-3_26

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-56891-9

  • Online ISBN: 978-3-540-47779-2

  • eBook Packages: Springer Book Archive

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