Trace-splitting for the parallel simulation of cache memory

  • Nicholas Ironmonger
Paper Sessions Architectures: Caches
Part of the Lecture Notes in Computer Science book series (LNCS, volume 694)


This paper presents two techniques enabling the trace-driven simulation of a single cache memory to be performed in parallel. They are both based on splitting the trace into sub-traces which are then separately applied to suitably modified versions of the cache simulator. The two techniques are called trace slicing and trace segmentation, after the way the trace is split, and require only large-grain parallelism. While simple, slicing leads to poor speedup due to the unbalanced distribution of references in a trace. Segmentation provides good speedup, as equations and implementation results demonstrate. For each segment, potential misses due to the unknown initial contents are recorded; the true status of these is determined at the end of the simulation. The techniques may be applicable to forms of trace-driven analysis other than cache simulation.


Cache Size Good Speedup Real Trace Cache Content Cache Design 
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  1. 1.
    A. Agarwal, M. Horowitz and J. Hennessy, “An Analytical Cache Model.” ACM Trans. on Computer Systems, 7, 2, May 1989, pp. 184–215.CrossRefGoogle Scholar
  2. 2.
    A. Agarwal, R. Sites and M. Horowitz, “ATUM: A New Technique for Capturing Address traces Using Microcode.” The 13th Annual Symposium on Computer Architecture, IEEE June 1986, pp. 119–127.Google Scholar
  3. 3.
    W.G. Alexander and D. B. Wortman, “Static and Dynamic Characteristics of XPL Programs.” Computer, 8, 11, Nov 1975, pp. 41–46.Google Scholar
  4. 4.
    A. Borg, R. E. Kessler and D. W. Wall, “Generation and Analysis of Very Long Address Traces.” The 17th Annual Symposium on Computer Architecture, IEEE, June 1990, pp. 270–279.Google Scholar
  5. 5.
    D. Clark, “Cache Performance in the VAX 11/780.” ACM Trans. on Computer Systems, 1, 1, Feb. 1983, pp. 24–37.Google Scholar
  6. 6.
    P. Heidelberger and H. S. Stone, “Parallel Trace-Driven Cache Simulation by Time Partitioning.” Proceedings of the 1990 Winter Simulation Conference, IEEE, pp. 734–737.Google Scholar
  7. 7.
    M. D. Hill and A. J. Smith, “Evaluating Associativity in CPU Caches.” IEEE Trans. on Computers, C-38, 12, December 1989, pp. 1612–1630.Google Scholar
  8. 8.
    S. Laha, J. H. Patel and R. K. Iyer, “Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems.” IEEE Trans. on Computers, C-37, 11, November 1988.Google Scholar
  9. 9.
    Y-B. Lin, J-L. Baer and E. D. Lazowska, “Tailoring a parallel trace-driven simulation technique to specific multiprocessor cache coherence protocols.” Distributed Simulation 1989, The Society for Computer Simulation, pp. 185–190.Google Scholar
  10. 10.
    A. Lunde, “Empirical Evaluation of Some Features of Instruction Set Processor Architectures.” CACM, 20, 3, Mar. 1977, pp. 143–153.Google Scholar
  11. 11.
    R. L. Mattson, J. Gecsei, D. R. Slutz and I. L. Traiger, “Evaluation Techniques for Storage Hierarchies.” IBM Systems Journal, 9, 2, 1970, pp. 78–117.Google Scholar
  12. 12.
    G. McDaniel, “An Analysis of a Mesa Instruction Set Using Dynamic Instruction Frequencies.” Proc. Symp. Architectural Support for Programming Languages and Operating Systems, ACM, Mar. 1982, pp. 167–176.Google Scholar
  13. 13.
    MIPS Computer Systems Inc., “Pixie”, MIPS Language Programmer's Guide. 1986.Google Scholar
  14. 14.
    A. J. Smith, “Cache memories.” ACM Trans. on Computer Systems, 14, 3, Sep. 1982, pp. 473–530.Google Scholar
  15. 15.
    H. S. Stone, “High-Performance Computer Architecture.” Addison-Wesley Publishing Co. 3rd. edition, 1993.Google Scholar
  16. 16.
    D. A. Wood, M. D. Hill and R. E. Kessler, “A Model for Estimating Trace-Sample Miss Ratios.” Proc. ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems, May 1991, pp. 79–89.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1993

Authors and Affiliations

  • Nicholas Ironmonger
    • 1
  1. 1.Seminar for Applied MathematicsETH ZurichZurichSwitzerland

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