During the past decade, microprocessor peak performance has increased at a tremendous rate using RISC concept, higher and higher clock frequencies and parallel/pipelined instruction issuing. As the gap between the main memory access time and the potential average instruction time is always increasing, it has become very important to improve the behavior of the caches, particularly when no secondary cache is used (i.e on all low cost microprocessor systems). In order to improve cache hit ratios, set-associative caches are used in some of the new superscalar microprocessors.
In this paper, we present a new organization for a multi-bank cache: the skewed-associative cache. Skewed-associative caches have a better behavior than set-associative caches: typically a two-way skewed-associative cache has the hardware complexity of a two-way set-associative cache, yet simulations show that it exhibits approximatively the same hit ratio as a four-way set associative cache of the same size.
Keywordsmicroprocessors cache set-associative cache skewed-associative cache
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