Petri Nets modeling in pipelined microprocessor design

  • Qian Zhang
  • Herbert Grünbacher
Project Papers
Part of the Lecture Notes in Computer Science book series (LNCS, volume 691)


In this paper, we propose a Petri nets modeling approach to support the design of pipelined processors. During the design process from instruction set to register transfer level (RTL), Petri nets are well suited to organize designer's ideas, illustrate processor structures, and present pipeline activities graphically. Early simulation helps error detection and evolution of the design. We first introduce how a block diagram may be modeled in marked timed Petri nets. The dynamic behavior of the model is then studied. Many pipeline design problems are directly visible from the simulation results. Rules for the assignment of initial markings of Petri Nets for synchronous circuits are given. Mapping Petri Net models to RTL models is shown. A RISC-like microprocessor with 30 instructions is used as an example.


Clock Cycle Program Counter Register Transfer Level Input Place Pipeline Design 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [EdPr92]
    W. Eder and H. Pristauz, “FUSE — A graphical simulation environment for pipelined designs”. In Proceedings of the 1992 European Simulation Multiconference (ESM 92), SCS June 1–3, 1992, pages 445–450.Google Scholar
  2. [HePa90]
    John L. Hennessy, David A. Patterson, Computer architecture: A quantitative approach, 1990, Morgen Kaufmann Publishers, Inc.Google Scholar
  3. [HoVe85]
    M. Holliday and M. Vernon, “A generalized timed Petri Net model for performance analysis”. In Proceedings of the International Workshop on Timed Petri Nets, Torino, Italy, July 1–3, 1985, pages 181–190.Google Scholar
  4. [Jenn91]
    G. Jenning, “GRTL — A graphical platform for pipelined system design”. In Proceedings of the 1991 European Conference on Design Automation (EDAC 1991), IEEE February 25–28, 1991, pages 424–428.Google Scholar
  5. [JeRo91]
    K. Jesen, G. Rozenberg (Eds), High-level Petri Nets, theory and applications. Springer-Verlag 1991Google Scholar
  6. [Kogg81]
    Petr M. Kogge, The architecture of pipelined computers. 1981, Hemisphere Publishing Corporation.Google Scholar
  7. [Mura89]
    T. Murata, “Petri Nets: properties, analysis and applications”. In Proceedings of the IEEE, Vol. 77, No. 4, April 1989, pages 541–580.Google Scholar
  8. [PIC90]
    PIC 16C5x series EPROM-based 8-bit CMOS microcontrollers, Microchip Technology Inc.Google Scholar
  9. [Razo88]
    R. R. Razouk, “The user of Petri Nets for modeling pipelined processors”. In Proceedings of the 25th Design Automation Conference, June 1988, pages 548–553.Google Scholar
  10. [Seit80]
    C. L. Seitz. System Timing. In CMead & L.Conway, Introduction to VLSI Systems, Chapter 7, 1980, Addison-Wesley.Google Scholar
  11. [Shap91]
    R. M. Shapiro, “Validation of a VLSI chip using hierarchical colored Petri Nets”. Microelectronics and Reliability, Special Issue on Petri Nets, Pergaman Press 1991.Google Scholar
  12. [Smit85]
    Connie U. Smith, “Robust models for the performance evaluation of software/hardware designs”. In Proceedings of the International Workshop on Timed Petri Nets, Torino, Italy, July 1–3, 1985, pages 172–180.Google Scholar
  13. [View91]
    VIEWLogic workview references, Viewlogic Systems, Inc., 1991.Google Scholar
  14. [Xiln91]
    The programmable gate array data book, Xilinx Inc., San Jose, 1991.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1993

Authors and Affiliations

  • Qian Zhang
    • 1
  • Herbert Grünbacher
    • 1
  1. 1.Institut für Technische InformatikVienna University of TechnologyViennaAustria

Personalised recommendations