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Better parallel architectures via emulations

  • Arnold L. Rosenberg
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 678)

Abstract

As the processors and communication subsystems of parallel architectures become progressively faster, it is becoming increasingly costeffective to build simple architectures that achieve complex behavior by emulating more complicated ones. We support this thesis by describing work by the author and collaborators [10] on algorithmically implementing, for pure SIMD bit-serial processor arrays, a multigauging capability that would be prohibitively expensive to implement in hardware.

Keywords

Parallel Architecture Complete Binary Tree Communication Subsystem Parallel Prefix Gauge Size 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1993

Authors and Affiliations

  • Arnold L. Rosenberg
    • 1
  1. 1.Department of Computer ScienceUniversity of MassachusettsAmherst

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