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From equations to hardware. Towards the systematic mapping of algorithms onto parallel architectures

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Parallel Image Analysis (ICPIA 1992)

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References

  1. [AAG*87] M. Annaratone, E. Arnould, T. Gross, H.T. Kung, M. Lam, O. Menzilcioglu, and J.A. Webb. The warp computer: architecture, implementation, and performance. IEEE tr. on Computers, C-36(12):1523–1538, December 1987. Systolique, Architecture parallele generale.

    Google Scholar 

  2. R. Airiau, J.-M. Bergé, V. Olive, and J. Rouillard. VHDL. Du langage à la modélisation. Collection Informatique, Presses Polytechniques et Universitaires Romandes, 1990.

    Google Scholar 

  3. A. Benveniste and G. Berry. The Synchronous Approach to Reactive and Real-Time Systems. PIEEE, 9(79):1270–1281, sep 1991.

    Google Scholar 

  4. [BCC*90] S. Borkar, R. Cohn, G. Cox, T. Gross, H.T. Kung, M. Lam, M. Levine, B. Moore, W. Moore, C. Peterson, J. Susman, J. Sutton, J. Urbanski, and J. Webb. Supporting Systolic and Memory Communication in i Warp. Technical Report, Carnegie Mellon University, 1990.

    Google Scholar 

  5. P. Boiras, D. Clément, Th. Despeyroux, J. Incerpi, G. Kahn, B. Lang, and V. Pascual. CENTAUR: the System. Technical Report 777, INRIA, 1987.

    Google Scholar 

  6. [DGL*91] C. Dezan, E. Gautrin, H. Le Verge, P. Quinton, and Y. Saouter. Synthesis of systolic arrays by equation transformations. In ASAP'91, IEEE, Barcelona, Spain, September 1991.

    Google Scholar 

  7. C. Dezan, H. Le Verge, P. Quinton, and Y. Saouter. The Alpha du Centaur environment. In P. Quinton and Y. Robert, editors, International Workshop Algorithms and Parallel VLSI Architectures II, North-Holland, Bonas, France, June 1991.

    Google Scholar 

  8. P. Frison and D. Lavenier. Experience in the design of parallel processor arrays. In International Workshop on Algorithms and Parallel VLSI Architectures II, Bonas (France), jun 1991.

    Google Scholar 

  9. P. Frison and D. Lavenier. A fully integrated systolic spelling co-processor. In VLSI91: International Conference on Very Large Scale Integration, August 1991.

    Google Scholar 

  10. D. Le Gall. MPEG: A Video Standard for Multimedia Applications. Communications of the ACM, 34(4):46–58, April 1991.

    Google Scholar 

  11. E. Gautrin and L. Perraudeau. Madmacs: a tool for the layout of regular arrays. In IFIP Workshop on Synthesis, Generation and Portability of Library Blocks for ASIC Design, March 1992.

    Google Scholar 

  12. John P. Hayes. Computer Architecture and Organization. Mc Graw Hill, New York, 1988.

    Google Scholar 

  13. C. Huizing, R. Gerth, and W. P. de Roever. Modelling Statecharts behaviour in a fully abstract way. In M. Dauchet and M. Nivat, editors, 13th Colloquium on Trees in Algebra and Programming CAAP'88, Lecture Notes in Computer Science, pages 271–294, Springer Verlag, Nancy, France, March 1988. Volume 299.

    Google Scholar 

  14. Dominique Lavenier. MicMacs: un réseau systolique linéaire programmable pour le traitement des chaines de caractères. PhD thesis, Université de Rennes 1, jun 1989.

    Google Scholar 

  15. D. Lavenier. A high performance systolic chip for spelling correction. In Euro Asic ' 92, pages 381–384, IEEE computer Society Press, jun 1992.

    Google Scholar 

  16. Paul Le Guernic, Thierry Gautier, Michel Le Borgne, and Claude Le Maire. Programming real-time applications with Signal. Proceedings of the IEEE, 79(9):1321–1336, septembre 1991.

    Google Scholar 

  17. H. Le Verge, C. Mauras, and P. Quinton. A language-oriented approach to the design of systolic chips. In International Workshop on Algorithms and Parallel VLSI Architectures, Pont-à-Mousson, June 1990. To appear in the Journal of VLSI Signal Processing, 1991.

    Google Scholar 

  18. H. Le Verge, C. Mauris, and P. Quinton. The ALPHA language and its use for the design of systolic arrays. Journal of VLSI Signal Processing, 3:173–182, 1991.

    Google Scholar 

  19. T. Mashburn, I. Lui, R. Brown, D. Cheung, G. Lum, and P. Cheng. Datapath: a cmos data path silicon assembler. In IEEE, editor, 23 rd Design Automation Conference, pages 722–729, 1986.

    Google Scholar 

  20. P. Quinton. The Systematic Design of Systolic Arrays. Technical Report, Microelectronics Center of North Carolina Research Report, July 1984.

    Google Scholar 

  21. P. Quinton. Systems of recurrence equations. In Conpar 9S-VAPP V Tutorial, Lyon (France), September 1992.

    Google Scholar 

  22. SOLO 1400 Reference Manual. ES2 Publication Unit, European Silicon Structures Limited, Berkshire, United Kingdom, 1990.

    Google Scholar 

  23. L. Thiele. Compiler techniques for massive parallel architectures. In P. Dewilde, editor, State of the Art in Computer Science, Kluwer Academic Publisher, 1992.

    Google Scholar 

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Akira Nakamura Maurice Nivat Ahmed Saoudi Patrick S. P. Wang Katsushi Inoue

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© 1992 Springer-Verlag Berlin Heidelberg

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Charot, F., Frison, P., Gautrin, E., Lavenier, D., Quinton, P., Wagner, C. (1992). From equations to hardware. Towards the systematic mapping of algorithms onto parallel architectures. In: Nakamura, A., Nivat, M., Saoudi, A., Wang, P.S.P., Inoue, K. (eds) Parallel Image Analysis. ICPIA 1992. Lecture Notes in Computer Science, vol 654. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-56346-6_25

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  • DOI: https://doi.org/10.1007/3-540-56346-6_25

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