Abstract
The Asynchronous Polycyclic Architecture (APA) is a new processor design for numerically intensive applications. APA resembles the VLIW architecture, in that it provides independent control and concurrent operation of low-level functional units within the processor. The main innovations of APA are the provision for multiple threads of control within each processor, the clustering of functional units into groups of functional units that show very weak coupling with each other, decoupled access/execute and eager execution. A supercomputer implementing this architecture is currently being designed, using commercially available parts.
This research was partly supported by the CNPQ grant 501971/91-2.
This is a preview of subscription content, log in via an institution to check access.
Preview
Unable to display preview. Download preview PDF.
Bibliography
Abu-Sufah, W and Mahoney, A. D., “Vector Processing on the Alliant FX/8 Processor”, Proc. Int'l Conf. Parallel Processing, 559–563, 1986.
Campos, G. L., Asynchronous Polycyclic Architecture, Proc. of the 12th Word Computer Congress, vol I-Algorithms, Software, Architecture, Sept 1992.
Chastain, M et al., “The Architecture of the CONVEX C240”, Proc. of the Fifth Conf. on Multiprocessors and Array Processors, 28–31, March 1989.
Dehnert, J. C., Hsu, P. Y. T., Bratt, J. P., “Overlapped Loop Support in the Cydra 5”, 3rd Int. Conf. on Architectural Support for Programming Languages and Operating Systems, 26–38, April 1989
Diede, T., et al. “The Titan Graphics Supercomputer Architecture”, IEEE Computer 21(9):13–30, September 1988.
Fisher, J. A. “Very Long Instruction Word Architectures and the ELI-512”, IEEE Conf. Proc. of the 10th Annual Int. Symp. on Comput. Architecture, 140–150, lune 1983.
Jouppi, N. P. and Wall, D. W., “Available Instruction-level Parallelism for Superscalar and Superpipelined Machines”, 3rd Int. Conference on Architectural Support for Programming Languages and Operating Systems, 272–282, April 1989.
Jouppi, N. P., “Architectural and Organizational Tradeoff in the Design of the MultiTitan CPU”, IEEE Conf. Proc. of the 16th Annual Int. Symp. on Comput. Architecture, 281–289, May 1989.
MCMAHON, F. H. “The Livermore Fortran Kernels: A Computer Test of the Numerical Performance Range,” Lawrence Livermore Nat'l Laboratory Report No. UCRL-53745, Livermore, CA, Dec. 1986.
McMahon, F. H. “The Livermore Fortran Kernels Test of the Numerical Performance Range”, in “Performance Evaluation of Supercomputers”, 143–186, edited by Martin, J. L., North Holland, 1988.
Oyang, Y. et al, “A Cost-Effective Approach to Implement a Long Instruction Word Microprocessor”, Computer Architecture News 18(1):59–72, March 1990.
Rau, B. R., Yen, D. W. L. and Towle, R. A. “The Cydra 5 Departmental Supercomputer”, IEEE Computer 22 (1):12–35, February 1989.
Smith, J. E., “Decoupled Access/Execute Architecture Computer Architectures”, ACM Trans. Computer Systems, 2(4):298–308, Nov 1984.
Smith, M. D., Johnson, M. and Horowitz, M. A. “Limits on Multiple Instruction Issue”, 3rd Int. Conference on Architectural Support for Programming Languages and Operating Systems, 290–302, April 1989.
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1992 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
de Campos, G.L. (1992). Asynchronous polycyclic architecture. In: Bougé, L., Cosnard, M., Robert, Y., Trystram, D. (eds) Parallel Processing: CONPAR 92—VAPP V. VAPP CONPAR 1992 1992. Lecture Notes in Computer Science, vol 634. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-55895-0_435
Download citation
DOI: https://doi.org/10.1007/3-540-55895-0_435
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-55895-8
Online ISBN: 978-3-540-47306-0
eBook Packages: Springer Book Archive