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A novel sorting array processor

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Parallel Processing: CONPAR 92—VAPP V (VAPP 1992, CONPAR 1992)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 634))

Abstract

Based on a novel array processor architecture, consisting of two tightly-coupled mesh-connected processing cells, a number of highly parallelizable sorting algorithms are realized by match the data flow with the interconnection topology. The sorting algorithms chosen are the odd-even sort, bitonic sort and binary tree sort. Taking the modularity of these algorithms, the array implementation of small sorting modules can be optimised, and nearly optimal sorters can then be constructed for large data sequences by cascading several small sorting modules together. With the novel architecture, vertical connections between cells in adjacent array layers provide additional versatility and expandability, compared with other sorting arrays. Techniques for realizing different sorting algorithms systematically will also been discussed.

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Authors and Affiliations

  1. School of Computing and Mathematical Sciences, Oxford Polytechnic, OX3 0BP, Headington, Oxford, UK

    Stephen P. S. Lam

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  1. Stephen P. S. Lam
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Luc Bougé Michel Cosnard Yves Robert Denis Trystram

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© 1992 Springer-Verlag Berlin Heidelberg

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Lam, S.P.S. (1992). A novel sorting array processor. In: Bougé, L., Cosnard, M., Robert, Y., Trystram, D. (eds) Parallel Processing: CONPAR 92—VAPP V. VAPP CONPAR 1992 1992. Lecture Notes in Computer Science, vol 634. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-55895-0_414

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  • DOI: https://doi.org/10.1007/3-540-55895-0_414

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-55895-8

  • Online ISBN: 978-3-540-47306-0

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