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Some remarks on the test complexity of iterative logic arrays

Extended abstract
  • Bernd Becker
  • Joachim Hartmann
Communications
Part of the Lecture Notes in Computer Science book series (LNCS, volume 629)

Abstract

The problem of detecting single cellular faults in arbitrarily large (one-dimensional, unilateral, combinational) iterative logic arrays (= ILAs) is considered. We prove that the test complexity of such an ILA is either constant or linear in the length of the ILA. The determination of the test complexity and the specification of the test set can be carried out by algorithms whose complexity only depends on the individual cell function of the ILA. Fault patterns which characterize any cellular fault are denned and their testability properties like (full, partial) testability, redundancy, test complexity are studied to give insight into the testability properties of the ILA under test construction.

Keywords

Testability Property Very Large Scale Integration Fault Pattern Input Combination Test Complexity 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    M. S. Abadir and H. K. Reghbati. Functional testing of semiconductor random access memories. Computing Surveys, 15:175–198, 1983.CrossRefGoogle Scholar
  2. [2]
    B. Becker and J. Hartmann. Optimal-time multipliers and c-testability. In Symp. on Parallel Algorithms and Architectures (SPAA'90), pages 174–179, 1990.Google Scholar
  3. [3]
    B. Becker and U. Sparmann. Computations over finite monoids and their test complexity. In 19th Int. Symp. on Fault-Tolerant Computing, pages 299–306, 1989.Google Scholar
  4. [4]
    B. Becker and U. Sparmann. A uniform test approach for RCC-Adders. In Proc. of the 3rd Aegean Workshop on Parallel Computation and VLSI Theory, Lecture Notes in Comp. Sci. 319, pages 288–300, 1988.MathSciNetCrossRefGoogle Scholar
  5. [5]
    M. Cappa and V.C. Hamacher. An augmented iterative array for high speed binary division. IEEE Trans. on Comp., C-22:172–176, 1973.Google Scholar
  6. [6]
    W.T. Cheng and J. H. Patel. Testing in two-dimensional iterative logic arrays. In Proc. of the 16th Int. Symp. on Fault Tolerant Computing Systems, pages 76–81, July 1986.Google Scholar
  7. [7]
    W. Daehn and J. Mucha. A hardware approach to self-testing of large PLA's. IEEE Trans. on Comp., C-30:829–833, 1981.Google Scholar
  8. [8]
    J. Ferguson and J.P. Chen. The design of two easily-testable VLSI array multipliers. In Proc. of the 6th Symp. on Computer Arithmetic, pages 2–9, June 1983.Google Scholar
  9. [9]
    A.D. Friedman. Easily testable iterative systems. IEEE Trans. on Comp., C-22:1061–1064, December 1973.Google Scholar
  10. [10]
    H. Fujiwara and K. Kinoshita. A design of programmable logic arrays with universal tests. IEEE Trans. on Comp., C-30(11):823–828, 1981.MathSciNetGoogle Scholar
  11. [11]
    F.C. Hennie. Iterative Arrays of Logical Circuits. M.I.T. Press, Cambridge, Mass., 1961.Google Scholar
  12. [12]
    W.H. Kautz. Testing for faults in combinational cellular logic arrays. In Proc. 5th Annual Symp. on Switching and Automata Theory, pages 161–1744, 1967.Google Scholar
  13. [13]
    T.W. Ku and M. Soma. Minimal overhead modification of iterative logic arrays for c-testability. In Proc. IEEE Int. Test Conf., pages 964–969, 1990.Google Scholar
  14. [14]
    B. Milne. Testability, 1985 technology forecast. Electronic Design, 10:143–166, 1985.Google Scholar
  15. [15]
    T. Sridhar and J.P. Hayes. Design of easily testable bit-sliced systems. In IEEE Trans. on Comp., pages 563–571, August 1981.Google Scholar
  16. [16]
    S.H. Unger. Pattern recognition using two dimensional, bilateral, iterative, combination, switching circuits. In Proc. Symp. Math. Theory of Automata, pages 577–591, April 1962.Google Scholar
  17. [17]
    A. Vergis and K. Steiglitz. Testability conditions for bilateral arrays of combinational cells. IEEE Trans. on Comp., C-35(1):13–22, January 1986.Google Scholar
  18. [18]
    C.D. Weiss. Optimal synthesis of arbitrary switching functions with regular arrays of two-input one-output switching elements. IEEE Trans. on Comp., C-18:839–856, September 1969.Google Scholar
  19. [19]
    T.W. Williams, W. Daehn, M. Grützner, and C.W. Starke. Comparison of aliasing errors for primitive and non-primitive polynomials. In Proc. IEEE Int. Test Conf., pages 282–288, 1986.Google Scholar
  20. [20]
    C.W. Wu and P.R. Capello. Easily testable iterative logic arrays. IEEE Trans. on Comp., C-39(5):640–652, May 1990.Google Scholar
  21. [21]
    H.J. Wunderlich. Hochintegrierte Schaltungen: Prüfgerechter Entwurf und Test. Springer Verlag, 1991.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1992

Authors and Affiliations

  • Bernd Becker
    • 1
  • Joachim Hartmann
    • 2
  1. 1.Computer Science DepartmentJ.W.G.-UniversityFrankfurtGermany
  2. 2.Computer Science DepartmentUniversity of SaarlandSaarbrückenGermany

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