Performance evaluation of cache memories in tightly coupled multiprocessor systems
The performance of several cache architectures of tightly coupled multiprocessor mainframes has been evaluated by trace-driven simulations. The traces were obtained on a monoprocessor running a transaction processing benchmark. These primary traces were then processed for use with multiprocessor simulations. This new method for providing multiprocessor traces has been validated by comparison with measurements.
One and two-level cache architectures for 1 to 8 processors have been modelled, in order to determine the miss ratios in caches up to 2 MB. Transaction processing is a very critical application for multiprocessors and the miss ratios here are about 4-times higher than with scientific applications. The influence of the coherence protocol on the cache performance is also analysed.
KeywordsCache Size Transaction Processing Instruction Cache Large Cache Cache Architecture
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