Performance evaluation of cache memories in tightly coupled multiprocessor systems

  • Jean-Marc Kuntz
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 605)


The performance of several cache architectures of tightly coupled multiprocessor mainframes has been evaluated by trace-driven simulations. The traces were obtained on a monoprocessor running a transaction processing benchmark. These primary traces were then processed for use with multiprocessor simulations. This new method for providing multiprocessor traces has been validated by comparison with measurements.

One and two-level cache architectures for 1 to 8 processors have been modelled, in order to determine the miss ratios in caches up to 2 MB. Transaction processing is a very critical application for multiprocessors and the miss ratios here are about 4-times higher than with scientific applications. The influence of the coherence protocol on the cache performance is also analysed.


Cache Size Transaction Processing Instruction Cache Large Cache Cache Architecture 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [Agar88a]
    Agarwal A., Hennessy J., Horowitz M., “Cache performance of operating system and multiprogramming workload”, ACM Transactions on Computer Systems, vol. 6, No. 4, p. 393–431, Nov. 1988CrossRefGoogle Scholar
  2. [Agar88b]
    Agarwal A., Simoni R., Hennessy J., Horowitz M., “An evaluation of directory schemes for cache coherence”, 15th Int. Symposium on Computer Architecture, p. 280–289, June 1988Google Scholar
  3. [ArBe86]
    Archibald J., Baer J.L., “Cache coherence protocols: evaluation using a multiprocessor simulation model”, ACM Trans. on Comp. Syst., vol. 4, No. 4, p. 273–298, Nov. 1986CrossRefGoogle Scholar
  4. [Bugge90]
    Bugge H.O., Kristiansen E.H., Bakka B.O., “Trace-driven simulations for a two-level cache design of open bus systems”, 17th Int. Symp. on Computer Architecture, p. 250–259, June 1990Google Scholar
  5. [Buss91a]
    Bussert W., “CPU-Referenzstrings von BS2000-Anwendungen”, Siemens Nixdorf internal report, Feb. 91, (german)Google Scholar
  6. [Buss91b]
    Bussert W., “Analyse der Cohit-Problematik auf Multiprozessor-Systeme”, 6th GI/TTG Measurement, Modelling & Evaluation of Computer Systems, Munich, Sept. 91 (short-paper in german)Google Scholar
  7. [Hill89]
    Hill M.D., Smith A.J., “Evaluating associativity in CPU caches”, IEEE Transactions on Computers, vol. 38, No. 12, p. 1612–30, Dec. 1989CrossRefGoogle Scholar
  8. [Lang91]
    Langendoen K.G., Muller H.L., Hertzberger L.O., “Evaluation of Futurebus hierarchical caching”, PARLE'91: Parallel Architectures and Language Europe, vol. 1, p. 52–68, June 1991Google Scholar
  9. [Short88]
    Short R.T., Levy H.M, “A simulation study of two-level caches”, 15th Int. Symp. on Computer Architecture, p. 81–88, June 1988Google Scholar
  10. [Sites88]
    Sites R.L., Agarwal A., “Multiprocessor cache analysis using ATUM”, 15th Int. Symp. on Computer Architecture, p. 186–195, June 1988Google Scholar
  11. [Smith82]
    Smith A.J., “Cache memories”, ACM Computing Surveys, vol. 14, p. 473–530, Sept. 1982CrossRefGoogle Scholar
  12. [Smith85]
    Smith A.J., “Cache evaluation and the impact of workload choice”, 12th Int. Symp. on Computer Architecture, p. 64–73, June 1985Google Scholar
  13. [Smith87]
    Smith A.J., “Line (block) size choice for CPU cache memories”, IEEE Trans. on Computers, vol.36, No. 9, p.1063–1075, Sept. 1987Google Scholar
  14. [Wang89]
    Wang W.H., “Multilevel cache hierarchies”, Ph.D. Dissertation, University of Washington, 1989Google Scholar
  15. [Wils90]
    Wilson A.W. Jr., “Multiprocessor cache simulation using hardware collected address traces”, 23th Hawaii Int. Conf. on Syst. Science, p. 252–260, 1990Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1992

Authors and Affiliations

  • Jean-Marc Kuntz
    • 1
    • 2
  1. 1.E.N.S.P. de Strasbourg 7Université Louis PasteurStrasbourg
  2. 2.Informationssysteme AGSiemens nexdorfMünchen 83

Personalised recommendations