Synthesis for testability: Binary Decision Diagrams

  • Bernd Becker
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 577)


We investigate the testability properties of Boolean circuits derived from (Reduced Ordered) Binary Decision Diagrams. It is shown that BDD-cirucits (or at least) BDD-like circuits are easily testable with respect to different fault models (cellular, stuck-at and path delay fault model). Furthermore the circuits and the test sets can be constructed efficiently.


VLSI structures algorithms and data structures synthesis (complete, full) testability fault model 


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Copyright information

© Springer-Verlag Berlin Heidelberg 1992

Authors and Affiliations

  • Bernd Becker
    • 1
  1. 1.Computer Science DepartmentJ.W.G.-UniversityFrankfurtGermany

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