Abstract
We have described the synthesis aspects of a design technique for delay insensitive circuits. The cornerstone of this technique is the language Synchronized Transitions. Programs in this language can be verified formally using tools supporting mechanical verification. In this paper we have described a tool for synthesizing delay insensitive circuits. Hence, we have demonstrated that it is feasible to use the same abstract description for both verification and synthesis.
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© 1992 Springer-Verlag Berlin Heidelberg
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Hulgaard, H., Christensen, P.H., Staunstrup, J. (1992). Synthesizing delay insensitive circuits from verified programs. In: Banâtre, J., Le Métayer, D. (eds) Reasearch Directions in High-Level Parallel Programming Languages. HLPPP 1991. Lecture Notes in Computer Science, vol 574. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-55160-3_53
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DOI: https://doi.org/10.1007/3-540-55160-3_53
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