A new partition lemma for planar graphs and its application to circuit complexity

Abstract

We consider the following combinatorial problem:

Given a planar graph. Some of its nodes are labelled by elements of given labelsets X _i , so that each label occurs at most t times. Can we find a “small” vertex set V* and “large” subsets Z _i ⊑ X _i , so that after deleting V* none of the remaining connected components contains labels from all sets Z _i .

Applying this result and the communication complexity model of multiparty protocols we prove that there are explicitly defined functions f _n := {0, 1}ⁿ → {0, 1} such that any multilective planar Boolean circuit computing f _n needs Ω(n(log n)²) gates, although these functions can be computed by linear-sized Boolean circuits.

This improves the separation of general circuits and multilective planar circuits due to Gy. Turán [7] by a factor of log n.

supported by the research grant of the Hungarian Academy of Sciences OTKA Nr. 2036