Advertisement

Optimal instruction scheduling using constraint logic programming

  • M. Anton Ertl
  • Andreas Krall
Session: Compiler Construction I
Part of the Lecture Notes in Computer Science book series (LNCS, volume 528)

Abstract

Instruction scheduling is essential for the efficient operation of today's and tomorrow's processors. It can be stated easily and declaratively as a logic program. Consistency techniques embedded in logic programming enable the efficient solution of this problem.

This paper describes an instruction scheduling program for the Motorola 88100 RISC processor, which minimizes the number of pipeline stalls. The scheduler is written in the constraint logic programming language ARISTO and uses a declarative model of the processor to generate an optimal schedule. The model uses lists of domain variables to represent the pipeline stages and describes the dependencies between instructions by constraints in order to ensure correct scheduling. Although optimal instruction scheduling is NP-complete, the scheduler can be applied to real programs because of the speed gained through consistency techniques.

Keywords

Logic Program Logic Programming Basic Block Pipeline Stage Register Allocation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [BEH91]
    David G. Bradlee, Susan J. Eggers, and Robert R. Henry. Integrating register allocation and instruction scheduling for RISCs. In Architectural Support for Programming Languages and Operating Systems, pages 122–131, 1991.Google Scholar
  2. [CNO+88]
    Robert P. Colwell, Robert P. Nix, John J. O'Donnel, David B. Papworth, and Paul K. Rodman. A VLIW architecture for a trace scheduling compiler. IEEE Transactions on Computers, 37(8):318–328, August 1988.Google Scholar
  3. [DSVH90]
    Mehmet Dincbas, Helmut Simonis, and Pascal Van Hentenryck. Solving large combinatorial problems in logic programming. The Journal of Logic Programming, (8):75–93, 1990.Google Scholar
  4. [Ert90]
    M. Anton Ertl. Coroutining und Constraints in der Logik-Programmierung. Master's thesis, Technische Universität Wien, 1990.Google Scholar
  5. [Fis81]
    Joseph A. Fischer. Trace scheduling: A technique for global microcode compaction. IEEE Transactions on Computers, 30(7):478–490, July 1981.Google Scholar
  6. [Gan89]
    Mahadevan Ganapathi. Prolog based retargetable code generation. Computer Languages, 14(3):193–204, 1989.Google Scholar
  7. [GH88]
    J. R. Goodman and W.-C. Hsu. Code scheduling and register allocation in large basic blocks. In International Conference on Supercomputing, 1988.Google Scholar
  8. [GM86]
    Phillip B. Gibbons and Steve S. Muchnick. Efficient instruction scheduling for a pipelined architecture. In Proceedings of the SIGPLAN '86 Symposium on Compiler Construction, pages 11–16, 1986.Google Scholar
  9. [HG83]
    John Hennessy and Thomas Gross. Postpass code optimization of pipeline constraints. ACM Transactions on Programming Languages and Systems, 5(3):422–448, July 1983.Google Scholar
  10. [Hu61]
    T. C. Hu. Paralell sequencing and assembly line problems. Operations Research, 9(6):841–848, 1961.Google Scholar
  11. [Kas90]
    Uwe Kastens. Übersetzerbau. R. Oldenbourg Verlag, München, 1990.Google Scholar
  12. [KN90]
    Andreas Krall and Ulrich Neumerkel. The Vienna Abstract Machine. In P. Deransart and J. Maluzyński, editors, Programming Language Implementation and Logic Programming (PLILP'90), pages 121–136. Springer LNCS 456, 1990.Google Scholar
  13. [Lam88]
    Monica Lam. Software pipelining: An effective scheduling technique for VLIW machines. In Proceedings of the SIGPLAN '88 Conference on Programming Language Design and Implementation, pages 318–328, 1988.Google Scholar
  14. [LKB91]
    Roland L. Lee, Alex Y. Kwok, and Fayé A. Briggs. The floating-point performance of a superscalar SPARC processor. In Architectural Support for Programming Languages and Operating Systems, pages 28–37, 1991.Google Scholar
  15. [Mot90]
    Motorola, Inc. MC88100 RISC Microprocessor User's Manual, second edition edition, 1990.Google Scholar
  16. [Nud83]
    Bernard Nudel. Consistent labeling problems and their algorithms: Expected complexities and theory-based heuristics. Artificial Intelligence, 21:135–178, 1983.Google Scholar
  17. [VH89]
    Pascal Van Hentenryck. Constraint Satisfaction in Logic Programming. Logic Programming Series. The MIT Press, Cambridge, Massachusetts, 1989.Google Scholar
  18. [VHD87]
    Pascal Van Hentenryck and Mehmet Dincbas. Forward checking in logic programming. In Logic Programming: Proceedings of the Fourth International Conference, pages 229–256, 1987.Google Scholar
  19. [Wal72]
    D. Waltz. Generating semantic descriptions from drawings of scenes with shadows. Technical report AI271, MIT, 1972.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1991

Authors and Affiliations

  • M. Anton Ertl
    • 1
  • Andreas Krall
    • 2
  1. 1.DMS Decision Management Systems Ges.m.b.H.Wien
  2. 2.Institut für ComputersprachenTechnische Universität WienWien

Personalised recommendations