A 30 Mbits/s (255,223) reed-solomon decoder

Abstract

The paper describes the VLSI implementation of a Reed-Solomon Coder-Decoder. This standard cell ASIC has been designed with VLSI Technology CAD tools on a SUN/4 workstation.

The chip includes two 256-byte ROM — table look-up for the inverse of field elements in GF(2⁸) —, one 512-byte RAM (buffer register) and the equivalent of 55 Kgates. The die size is 440 mils × 440 mils and the process used for manufacturing is CMOS 1.0 µ.

The Reed-Solomon code is a (N,N-32) block code of 8-bit symbols capable of correcting up to v symbol errors and ρ symbol erasures provided that 2v+ρ≤32. N assumes values less than or equal to 255 (when N<255 a shortened code is generated).

The data rate achieved by the decoder depends on the dimension K of the code selected and equals K÷256×34 Mbits/s (34 MHz is the maximum frequency corresponding to the industrial worst case). For example the (255,223)RS operates at 30 Mbits/s compared to the (64,32) RS operating at 4,2 Mbits/s.