Systolic architectures for multiplication over finite field GF(2^m)

Abstract

In this paper, we develop two systolic architectures for the productsum computation P=AB+C in the finite field GF(2 ^m). The multipliers consist of m basic cells arranged into a serial-in, serial-out one-dimensional systolic array. They need only one control signal. The first multiplier is semi-serial (coefficient B is input in parallel), and performs simultaneously two product-sum computations P=AB+C and P′=A′B+C′. The bits of the coefficients A, C, A′, C′ are received serially. The bits of the results P and P' are generated serially. The second multiplier is serial (coefficients A, B, and C are input serially), and performs one product-sum computation at a time. The bits of the coefficients A, B, and C are received serially. The bits of the result P are generated serially. In all the cases, the architectures are simple, regular, and possess the properties of concurrency and modularity. As a consequence, they are well suited for VLSI design.