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Parallel computers and parallel computing in scientific simulations

  • Tsutomu Hoshino
Invited Lectures
Part of the Lecture Notes in Physics book series (LNP, volume 323)

Abstract

Users are recommended to know more about the computer architectures and to benchmark the machines before falling in love with a particular machine, unless he/she is willing to die for that love. Even the users' participation in the designing phase of the machine is encouraged, in order to make the end product practical in their applications, otherwise they have to be patient in using the unfriendly machine.

Will future be a peaceful world in which several types of parallel machines coexist, or a battle field where they fight for a share in the market? Somewhat between the both extremes could be anticipated. Decisive factor for the future world will again come from the basic technology of logic devices (silicon and its successors), and of integrating them.

Superconduction may be an important but not decisive factor in speeding-up the machines, if it is solely used for the signal transmission in the computer hardware. The delay in the present computer circuit is caused by the high impedance in the logic device and the stray capacity along the transmission line, where the superconducting line helps little in speeding-up. It is still difficult to predict what the superconductive logic device and its integration will be.

Optical technology may be more important to breakthrough the pinnumber-limitation, often hindering some of the parallel architectures with massive connection. The introduction of optical technology in inter-board or inter-logic device connection will push the computer architecture toward more parallelism and higher efficiency.

Keywords

Parallel Computer Parallel Machine Computer Architecture Logic Device Vector Processing 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    Harold S. Stone, High-Performance Computer Architecture, Addison-Wesley, 1987.Google Scholar
  2. [2]
    T. Hoshino, An invitation to the world of PAX, IEEE Computer 9 (1986) 68–79.Google Scholar
  3. [3]
    T. Hoshino, T. Shirakawa and K. Tsuboi, Mesh-connected parallel computer PAX for scientific applications, Parallel Computing 5 (1987)363–371.Google Scholar
  4. [4]
    T. Hoshino, T. Kamimura, T. Iida and T. Shirakawa, Parallelized ADI scheme using GECR (Gauss-elimination-cyclic-reduction) method and implementation of Navier-Stokes equation in the PAX computer, Proc. 1985 International Conference on Parallel Processing (IEEE Computer Society Press, Silversprings, 1985) 426–433.Google Scholar
  5. [5]
    T. Hoshino R. Hiromoto, S. Sekiguchi and S. Majima, Mapping schemes of the particle-in-cell method implemented on the PAX computer, to be published in Parallel Computing. *** DIRECT SUPPORT *** A3418252 00002Google Scholar

Copyright information

© Springer-Verlag 1989

Authors and Affiliations

  • Tsutomu Hoshino
    • 1
  1. 1.Institute of Engineering MechanicsUniversity of TsukubaTsukuba-shi, Ibaraki-kenJapan

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