Running order statistics on a bit-level systolic array

  • N. Petkov
Submitted Papers
Part of the Lecture Notes in Computer Science book series (LNCS, volume 342)


A two-dimensional bit-level systolic array for running order statistics is presented. Both word-level and bit-level parallelism are employed. The array is extremely easy to implement in VLSI, because its cells are very small and simple. Since extensive pipe-lining is used at both word and bit level, the array can be operated at very high clock frequencies achieving very high throughputs. The algorithm delivers full running order statistics in time ϑ(n) and area ϑ[n(w+logn)] where n is the cardinality of the processed set and w is the word width of its elements.

Index terms

running order statistics bit-level systolic arrays VLSI 


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Copyright information

© Springer-Verlag Berlin Heidelberg 1989

Authors and Affiliations

  • N. Petkov
    • 1
  1. 1.Central Institute of Cybernetics and Information ProcessesInt'l Lab. Image Processing & Computer GraphicsBerlin

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