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Multiprocessor arrays: Topology, efficiency and fault-tolerance

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Parcella '88 (Parcella 1988)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 342))

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Abstract

Starting from categories of the known computer-networks-area like message-handling, bus, protocol etc. may lead to a dead-end with respect to multiprocessor-design. Those terms from the world of networks may persuade computer architects to choose solutions which are not adequate to the requirements of efficient and fault-tolerant operation.

Topological investigations including technological considerations will result in structures which differ contrarily from the traditional monoprocessor as well as from computer networks. The macro-dataflow-concept [11] for instance can ensure in the framework of the usual storage-access a high rate of efficiency. Also, system programming and application programming will not deviate in this case too much from the traditional patterns. Beyond it the approaches for fault-tolerant operation become then simple and effective.

Experiences with multiprocessors, which are accordingly designed are discussed.

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Authors and Affiliations

  1. Institut für Mathematische Maschinen und Datenverarbeitung (Informatik III), Universität Erlangen-Nürnberg, Martensstraße 3, D-8520, Erlangen

    Prof. em. Dr. Wolfgang Händler

Authors
  1. Prof. em. Dr. Wolfgang Händler
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Gottfried Wolf Tamáas Legendi Udo Schendel

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© 1989 Springer-Verlag Berlin Heidelberg

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Händler, W. (1989). Multiprocessor arrays: Topology, efficiency and fault-tolerance. In: Wolf, G., Legendi, T., Schendel, U. (eds) Parcella '88. Parcella 1988. Lecture Notes in Computer Science, vol 342. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-50647-0_100

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  • DOI: https://doi.org/10.1007/3-540-50647-0_100

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  • Print ISBN: 978-3-540-50647-8

  • Online ISBN: 978-3-540-46062-6

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