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Combined Formal Post- and Presynthesis Verification in High Level Synthesis

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Formal Methods in Computer-Aided Design (FMCAD 1998)

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Abstract

We propose a formal framework based on higher order logic theorem proving as a support for high level synthesis. We suppose that the design process starts from a behavioural or functional specification in terms of a VHDL description. It produces a structural description at the register transfer level. We propose a method for proving the correctness of synthesis results combining the advantages of presynthesis and postsynthesis verification. To perform the postsynthesis task automatically and efficiently correctness-implying properties of an intermediate synthesis result are checked.

This work is supported by the Deutsche Forschungsgemeinschaft under project no. GR 1006/21 (FORVERTIS)

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Lock, T., Mendler, M., Mutz, M. (1998). Combined Formal Post- and Presynthesis Verification in High Level Synthesis. In: Gopalakrishnan, G., Windley, P. (eds) Formal Methods in Computer-Aided Design. FMCAD 1998. Lecture Notes in Computer Science, vol 1522. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-49519-3_16

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  • DOI: https://doi.org/10.1007/3-540-49519-3_16

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