Generation of Test Patterns for Differential Diagnosis of Digital Circuits

Abstract

Objective. In a faulty digital circuit, many (single) faulty gates may explain the observed findings. It may be not practical (e.g. in VLSI chips) to test points in the circuit other than their input and output bits, so constraint technology was used to obtain input patterns that identify single faulty gates. However, two alternative faulty gates often have a large number of test patterns, but only a few, if any, differentiate them. We focus on obtaining test patterns that discriminate alternative faulty gates. Technique. The technique of [2] to generate a test pattern for a faulty gate introduces new values, d and notd, and assigns d to the gate output. New truth tables cope with the new values, and the patterns generated force a d (or notd) to reach an output bit

We adapted the technique to differentiate two faulty gates, not both faulty. The output of a gate is either independent of the faulty state of both gates, or depends on the faulty state of one of the gates alone or depends on either faulty states. We denote this latter case as m-X, meaning that the gate output takes value X if both gates are normal and not X if any of the gates is faulty. Similarly, d1-X (d2-X) denotes the output of a gate that depends solely on the faulty state of gate g₁ (g₂) and takes value X if g₁ (g₂) is normal and not X if it is faulty. We developed truth tables to cope with these new values, which depend on whether the gate is one of the potentially faulty.