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The Influence of Architectural Parameters on the Performance of Parallel Logic Programming Systems

  • Marcio G. Silva
  • Inês C. Dutra
  • Ricardo Bianchini
  • Vítor Santos Costa
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1551)

Abstract

In this work we investigate how different machine settings for a hardware Distributed Shared Memory (DSM) architecture affect the performance of parallel logic programming (PLP) systems. We use execution-driven simulation of a DASH-like multiprocessor to study the impact of the cache block size, the cache size, the network bandwidth, the write buffer size, and the coherence protocol on the performance of Andorra-I, a PLP system capable of exploiting implicit parallelism in Prolog programs. Among several other observations, we find that PLP systems favour small cache blocks regardless of the coherence protocol, while they favour large cache sizes only in the case of invalidate-based coherence. We conclude that the cache block size, the cache size, the network bandwidth, and the coherence protocol have a significant impact on the performance, while the size of the write buffer is somewhat irrelevant.

Keywords

DSM architectures performance evaluation logic programming 

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Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • Marcio G. Silva
    • 1
  • Inês C. Dutra
    • 1
  • Ricardo Bianchini
    • 1
  • Vítor Santos Costa
    • 2
  1. 1.COPPE/Systems EngineeringFederal University of Rio de JaneiroBrazil
  2. 2.LIACC and DCC-FCUPPortoPortugal

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