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International Conference of the Austrian Center for Parallel Computation

ACPC 1999: Parallel Computation pp 211–225Cite as

On Parallel Reconfigurable Architectures for Image Processing

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1557))

Abstract

This paper proposes a short overview analysing the adequation between image processing requirements, parallel reconfigurable architectures dedicated to image processing and parallel computing. Through some examples of academic prototypes and commercialised computers the evolution of concepts useful for efficient and real time image processing is shown.

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Author information

Authors and Affiliations

  1. Laboratoire de Robotique de Paris (LRP), CNRS, 10-14, avenue de l’Europe, 78 140, Vélizy, France

    Edwige Pissaloux

  2. Faculté des Sciences, Université de Rouen, 76 821, Mont Saint Aignan, France

    Edwige Pissaloux

Authors
  1. Edwige Pissaloux
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Editor information

Editors and Affiliations

  1. Forschungsinstitut für Softwaretechnologie, Hellbrunnerstr. 34, A-5020, Salzburg, Austria

    Peter Zinterhof

  2. Slovac Academy of Sciences, Institute of Mathematics, Laboratory for Informatics, Dubravska 9, P.O.Box 56, 840 00, Bratislava, Slovakia

    Marian Vajteršic

  3. Universität Salzburg, RIST++, Hellbrunnerstr. 34, A-5020, Salzburg, Austria

    Andreas Uhl

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© 1999 Springer-Verlag Berlin Heidelberg

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Pissaloux, E. (1999). On Parallel Reconfigurable Architectures for Image Processing. In: Zinterhof, P., Vajteršic, M., Uhl, A. (eds) Parallel Computation. ACPC 1999. Lecture Notes in Computer Science, vol 1557. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-49164-3_20

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  • DOI: https://doi.org/10.1007/3-540-49164-3_20

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-65641-8

  • Online ISBN: 978-3-540-49164-4

  • eBook Packages: Springer Book Archive

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