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Architectural Approaches for Multimedia Processing

Invited Paper

  • Conference paper
  • First Online:
Parallel Computation (ACPC 1999)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1557))

Abstract

The recent advances in VLSI technology, high-speed processor designs, Internet/Intranet implementations, broadband networks (ATM and ISDN) and compression standards (JPEG, MPEG, H.261, H.263 and G.273) are leading to the popularity of multimedia applications. Examples include, video over the internet, interactive TV, distance learning, telemedicine, and digital libraries. Multimedia refers to a combination of various media types including text, audio, 2D and 3D graphics, animation, images and video. Visual media (image, video and graphics) proliferation in multimedia applications demands high-powered compute engines, large storage devices, and high bandwidth networks for processing, storage, and transport of image/video data. Visual media processing poses challenges from several perspectives, specifically from the points of view of real-time implementation and scalability. There has been several approaches to obtain speedups to meet the computing demands in multimedia processing ranging from media processors to special purpose implementations. Note that a variety of parallel processing strategies are adopted in these implementations in order to achieve the required speedups. The objective of this paper to present a summary of the various architectural alternatives that exist for multimedia processing.

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References

  1. D. L. Gall, “MPEG: A Video compression Standard for Multimedia Applications’, Communications of the ACM, Vol. 34, No. 4, April 1991, pp. 59–63.

    Article  Google Scholar 

  2. ITU-T Recommendation H.263. “Video Coding for Low Bitrate Communication’, October 1995.

    Google Scholar 

  3. ISO/IEC JTC1/SC29/WG11, “Information Technology-Coding of Audio-Visual Objects. Visual ISO/IEC 14496-2 Committee Draft.’ Fribourg, October 1997.

    Google Scholar 

  4. “MPEG-7 FAQ”, http://drogo.cselt.stet.it/mpeg/faq/faq_mpeg-7.htm.

  5. K. Aizawa and T. S. Huang, “Model-Based Image Coding: Advanced Video Coding Techniques for Very Low Bit-Rate Applications”, Proceedings of the IEEE, Vol. 83, No. 2, February 1995, pp. 259–271.

    Article  Google Scholar 

  6. “LSI Logic Consumer Products”, http://www.lsilogic.com/products/unit5_6z.html.

  7. S. Bose, “A single chip multi-standard video codec”, Proceedings IEEE Hot Chips V, Stanford CA, Aug. 1993.

    Google Scholar 

  8. Phil Bernosky and Scott Tandy, “Bringing Workstation Graphics Performance to a Desktop Near You: ViRGE/VX“, Proceedings IEEE Hot Chips 8, Stanford CA, Aug. 1996. http://infopad.eecs.berkeley.edu/HotChips8/9.2/.

  9. “8x8’s Video Communication Processor“, http://www.8x8.com/docs/chips/vcp.html.

  10. Michael Kagan, “P55C Micro-Architecture: The First Implementation of the MMX Technology”, Proceedings IEEE Hot Chips 8, Stanford CA, Aug. 1996.

    Google Scholar 

  11. “MediaGX Architectural System Overview”, http://www.cyrix.com/process/prodinfo/mediagx/gxovervw.htm.

  12. Gerrit Slavenburg, Selliah Rathnam, and Henk Dijkstra, “The TriMedia TM-1 PCI VLIW Media Processor”, Proceedings IEEE Hot Chips 8, Stanford CA, Aug. 1996.

    Google Scholar 

  13. D. Patterson, T. Anderson, and K. Yelick, “A Case for Intelligent RAM: IRAM”, Hot chip 8, 1996.

    Google Scholar 

  14. J. Hennessy and D. Patterson, Computer Organization and Design, Morgan Kaufmann Publisher, 1994.

    Google Scholar 

  15. T. Sunaga, H. Miyatake, K. Kitamura, P. Kogge, and Eric Retter, “A parallel processing chip with embedded DRAM macros”, IEEE Journal of Solid-State Circuits, pp. 1556–1559, vol. 31, no. 10, Oct. 1996.

    Article  Google Scholar 

  16. D. G. Elliott, M. Snelgrove, and M. Stumm, “Computational-RAM: A Memory-SIMD Hybrid and Its Applications to DSPs”, IEEE Custom Integrated Circuits Conference, pp. 30.6.1–30.6.4, Boston, May 1992.

    Google Scholar 

  17. C. Cojocaru, Computational-RAM: Implementation and Bit-Parallel Architecture, Master’s dissertation, Department of Electronics, Carleton University, Dec. 1994.

    Google Scholar 

  18. N. Yamashita, T. Kimura, Y. Fujita, Y. Aimoto, “A 3.84 GIPS Integrated Memory Array Processor LSI with 64 Processing Elements and 2Mb SRAM”, ISSCC’94, pp. 202–203, 1994.

    Google Scholar 

  19. C. Cojocaru, Computational-RAM: Implementation and Bit-Parallel Architecture, Master’s dissertation, Department of Electronics, Carleton University, Dec. 1994.

    Google Scholar 

  20. M. Gokhale, B. Holmes, and K. Iobst, “Processing in Memory: The Terasys Massively Parallel PIM Array”, IEEE Computer, 28(3), pp. 23–31, Apr. 1995.

    Google Scholar 

  21. D. Hammerstrom and D. Lulich, “Image Processing Using One-Dimensional Processor Arrays”, Proceedings of the IEEE, vol. 84, no. 7, pp. 1005–1018, Jul. 1996.

    Article  Google Scholar 

  22. Y. Aimoto, T. Kimura, Y. Yabe, “A 7.68GIPS 3.84GB/s 1W Parallel Image Processing RAM integrating a 16Mb DRAM and 128 Processors”, ISSCC’96, pp. 372–373, 1996.

    Google Scholar 

  23. J. Gealow, F. Herrmann, L. Hsu, and C. Sodini, “System Design for Pixel-Parallel Image Processing”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 4, no. 1, pp. 32–41, Mar. 1996.

    Article  Google Scholar 

  24. R. Foss, “Implementing Application Specific Memory”, ISSCC’96, Paper FP 16.1, 1996.

    Google Scholar 

  25. R.N. McKenzie, W.M. Snelgrove, and D.G. Elliott, “A 1024 Processing-Element Computational RAM”, TRIO, Kingston, May 1997.

    Google Scholar 

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Author information

Authors and Affiliations

  1. Visual Computing and Communications Laboratory Department of Computer Science and Engineering, Arizona State University, P.O. Box 875406, Tempe, AZ 85287-5406

    Sethuraman (Panch) Panchanathan (Senior Member IEEE)

Authors
  1. Sethuraman (Panch) Panchanathan
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Editor information

Editors and Affiliations

  1. Forschungsinstitut für Softwaretechnologie, Hellbrunnerstr. 34, A-5020, Salzburg, Austria

    Peter Zinterhof

  2. Slovac Academy of Sciences, Institute of Mathematics, Laboratory for Informatics, Dubravska 9, P.O.Box 56, 840 00, Bratislava, Slovakia

    Marian Vajteršic

  3. Universität Salzburg, RIST++, Hellbrunnerstr. 34, A-5020, Salzburg, Austria

    Andreas Uhl

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© 1999 Springer-Verlag Berlin Heidelberg

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Panchanathan, S.(. (1999). Architectural Approaches for Multimedia Processing. In: Zinterhof, P., Vajteršic, M., Uhl, A. (eds) Parallel Computation. ACPC 1999. Lecture Notes in Computer Science, vol 1557. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-49164-3_19

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  • DOI: https://doi.org/10.1007/3-540-49164-3_19

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-65641-8

  • Online ISBN: 978-3-540-49164-4

  • eBook Packages: Springer Book Archive

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