Abstract
With rapid advances in FPGA and other hardware technologies, architectures based on configurable computing engines, in which the Arithmetic Logic Unit (ALU) can be modified on-the-fly during computation, are becoming popular. Configurable architectures offer an opportunity for adapting the underlying hardware to the computation for efficiency. Typically, the need for configuration arises due to the fact that a given hardware ALU configuration is better suited for execution of a given algorithmic step. Since a program is an abstraction of a sequence of algorithmic steps, the need for such a reconfiguration (i.e., changing from one configuration to another), would thus, arise at different program points corresponding to these algorithmic steps. The problem of identifying the optimal configurations at different steps in a program is a very complex issue but allows the power of these architectures to be maximally used if solved. The success of these architectures critically depends on the effectiveness of the compiler and the research in this area is just beginning. The purpose of this paper is to specifically focus on an automatic compilation framework developed to effectively exploit operator parallelism.
This work is supported by the DARPA contract ARMY DABT63-97-C-0029
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© 1999 Springer-Verlag Berlin Heidelberg
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Ramasubramanian, N., Subramanian, R., Pande, S. (1999). Automatic Analysis of Loops to Exploit Operator Parallelism on Reconfigurable Systems. In: Chatterjee, S., et al. Languages and Compilers for Parallel Computing. LCPC 1998. Lecture Notes in Computer Science, vol 1656. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48319-5_20
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DOI: https://doi.org/10.1007/3-540-48319-5_20
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