A Fault Tolerant Clock Synchronization Algorithm for Systems with Low-Precision Oscillators
In this paper we present a new fault tolerant clock synchronization algorithm, the Fault Tolerant Daisy Chain algorithm. It is intended for internal clock synchronization of systems using a broadcast bus with Time Division Multiple Access (TDMA) communication, or other systems where clock readings are broadcast at regular intervals. The algorithm allows synchronization after each clock reading and is therefore tolerant to oscillators with large drift rates. Clock hardware is simplified since it is not necessary to store the collected clock readings until the next synchronization, nor is it necessary to schedule synchronization events. Theoretical bounds on clock skew are derived assuming non-Byzantine and Byzantine faults and compared with three different convergence synchronization algorithms. A simulated fault injection study is also presented, where the proposed algorithm was found to tolerate transient faults better than the theoretically best among the convergence algorithms, particularly at high drift rates.
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