Concurrent Detection of Processor Control Errors by Hybrid Signature Monitoring
In this study, we present a new concurrent error-detection scheme by hybrid signature to the on-line detection of control flow errors caused by transient and intermittent faults. The proposed hybrid signature monitoring technique combines the vertical signature scheme with the horizontal signature scheme. We first develop a new vertical signature scheme. The length of vertical signature is adjustable. The attribute of adjustable length can be employed to reduce the length of vertical signature, but at meantime it also decreases the coverage. The rest of signature word can be utilized for the horizontal signature and recording the block length. The horizontal signature can offset the coverage degradation due to the reduction of vertical signature length, and decrease the latency significantly. The simulation is conducted to justify the effectiveness of the proposed technique and compared with the previous schemes.
The main contribution of this research is to integrate the vertical signature, horizontal signature and watchdog timer techniques into a single signature word, and without the using of the memory system equipped with the SECDED code. Therefore, with no increase or even lower of memory space overhead and watchdog processor complexity, our scheme has higher errordetection coverage and much shorter error-detection latency compared with the previous representative techniques.
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