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A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits

  • Tomasz Garbolino
  • Andrzej Hlawiczka
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1667)

Abstract

In the paper authors analyse properties of the various structures of linear registers (LFSRs) that are used as the test pattern generators in VLSI circuits. It is shown that the majority of them have one or more of the following drawbacks:
  • large area overhead that is caused by the large number of XOR gates,

  • reduced operational frequency due to presence of the long connection in the main feed-back loop and the high fan-out on the outputs of the flip-flops,

  • inflexible structure that cannot be easily redesigned and adjusted to the needs of the digital circuit efficient testing.

In the paper we present a new type of LFSR that is free from all mentioned above disadvantages. We also develop the algebraic description of its operation and the methods of its designing. Finally we give numerous examples of its structures for different lengths of the register.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1999

Authors and Affiliations

  • Tomasz Garbolino
    • 1
  • Andrzej Hlawiczka
    • 1
  1. 1.Institute of ElectronicsSilesian Technical University of GliwiceGliwicePOLAND

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