A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits
large area overhead that is caused by the large number of XOR gates,
reduced operational frequency due to presence of the long connection in the main feed-back loop and the high fan-out on the outputs of the flip-flops,
inflexible structure that cannot be easily redesigned and adjusted to the needs of the digital circuit efficient testing.
In the paper we present a new type of LFSR that is free from all mentioned above disadvantages. We also develop the algebraic description of its operation and the methods of its designing. Finally we give numerous examples of its structures for different lengths of the register.
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