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Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks

  • M. Bellos
  • D. Nikolos
  • H. T. Vergos
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1667)

Abstract

In this paper we consider path delay fault testing of a class of isomorphic Multistage Interconnection Networks (MINs) with centralized control using as representative the nxn Omega network. We show that the number of paths is 3n2-2n and we give a method for testing those applying only 2(3n-2) pairs of test vectors. We also show that this is the least number of test vector pairs that are required for testing all paths of the MIN. We also give a path selection method such that: a) the number of selected paths, that is, the number of paths that must be tested, is a small percentage of all paths and the propagation delay along every other path can be calculated from the propagation delays along the selected paths, b) all the selected paths are tested by using 2(3log2n+1) test vector pairs. Both methods derive strong delay—verification test sets.

Keywords

Control Input Propagation Delay Test Vector Delay Fault Circuit Under Test 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1999

Authors and Affiliations

  • M. Bellos
    • 1
  • D. Nikolos
    • 1
    • 2
  • H. T. Vergos
    • 1
    • 2
  1. 1.Dept. of Computer Engineering and InformaticsUniversity of PatrasRioGreece
  2. 2.Computer Technology InstitutePatrasGreece

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