Exploiting Retiming in a Guided Simulation Based Validation Methodology

  • Aarti Gupta
  • Pranav Ashar
  • Sharad Malik
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1703)


There has been much interest recently in combining the strengths of formal verification techniques and simulation for functional validation of large designs [6].Typically, a formal test model is first obtained from the design. Then, test sequences which satisfy certain coverage criteria are generated from the test model, which are simulated on the design for functional validation. In this paper, we focus on automatic abstractions for obtaining the test model from the design for simulation vector generation under the transition tour coverage model. Since most efforts using guided simulation have concentrated only on state/transition coverage, without relating these to error coverage of the original design, there is hardly any notion of preserving correctness, which has made it hard to use abstraction effectively.


  1. 1.
    A. Balakrishnan and S. T. Chakradhar. Software transformations for sequential test generation. In Fourth Asian Test Symposium, 1995.Google Scholar
  2. 2.
    P. Franzon. Digital computer technology and design: Fall 1994 project. Private Communication, 1996.Google Scholar
  3. 3.
    A. Gupta, S. Malik, and P. Ashar. Toward formalizing a validation methodology using simulation coverage. In Proc. 34th Design Automation Conf., pages 740–745, June 1997.Google Scholar
  4. 4.
    R. Gupta, R. Gupta, and M. A. Breuer. BALLAST: A methodology for partial scan design. In Proceedings of the International Symposium on Fault Tolerant Computing, pages 118–125, June 1989.Google Scholar
  5. 5.
    J. L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann, 1990.Google Scholar
  6. 6.
    R. C. Ho, C. H. Yang, M. A. Horowitz, and D. L. Dill. Architecture validation for processors. In Proc. 22nd Annual International Symposium on Computer Architecture, June 1995.Google Scholar
  7. 7.
    Charles E. Leiserson and James B. Saxe. Retiming Synchronous Circuitry. Algorithmica, 6(1):5–36, 1991.zbMATHCrossRefMathSciNetGoogle Scholar
  8. 8.
    S. Malik, E. Sentovich, R. K. Brayton, and A. Sangiovanni-Vincentelli. Retiming and resynthesis: Optimizing sequential networks with combinational techniques. IEEE Tran. on CAD of Integrated Circ. and Sys., 10(1): 74–84, Jan. 1991.CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1999

Authors and Affiliations

  • Aarti Gupta
    • 1
  • Pranav Ashar
    • 1
  • Sharad Malik
    • 2
  1. 1.CCRLNEC USAPrincetonUSA
  2. 2.Princeton UniversityPrincetonUSA

Personalised recommendations