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Refinement and Property Checking in High-Level Synthesis Using Attribute Grammars

  • George Economakos
  • George Papakonstantinou
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1703)

Abstract

Recent advances in fabrication technology have pushed the digital designers’ perspective towards higher levels of abstraction. Previous work has shown that attribute grammars, used in traditional compiler construction, can also be effectively adopted to describe in a formal and uniform way high-level hardware compilation heuristics, their main advantages being modularity and declarative notation. In this paper, a more abstract form of attribute grammars, relational attribute grammars, are further applied as a framework over which formal hardware verification is performed along with synthesis. The overall hardware design methodology proposed is a novel idea that supports provable correct designs.

Keywords

Parse Tree Semantic Condition Behavioral Description Attribute Grammar Nonterminal Symbol 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1999

Authors and Affiliations

  • George Economakos
    • 1
  • George Papakonstantinou
    • 1
  1. 1.Dept. of Electrical and Computer EngineeringNational Technical University of AthensGreece

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