Program Slicing of Hardware Description Languages

  • E. M. Clarke
  • M. Fujita
  • S. P. Rajan
  • T. Reps
  • S. Shankar
  • T. Teitelbaum
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1703)


Hardware description languages (HDLs) are used today to describe circuits at all levels. In large HDL programs, there is a need for source code reduction techniques to address a myriad of problems in formal verification, design, simulation, and testing. Program slicing is a static program analysis technique that allows an analyst to automatically extract portions of programs relevant to the aspects being analyzed. We extend program slicing to HDLs, thus allowing for automatic program reduction to allow the user to focus on relevant code portions. We have implemented a VHDL slicing tool composed of a general inter-procedural slicer and a front-end that captures VHDL execution semantics. This paper provides an overview of program slicing, a discussion of how to slice VHDL programs, a description of the resulting tool, and a brief overview of some applications and experimental results.


Model Check Dependence Graph Program Point Control Flow Graph Graph Reachability 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1999

Authors and Affiliations

  • E. M. Clarke
    • 1
    • 6
  • M. Fujita
    • 3
  • S. P. Rajan
    • 3
  • T. Reps
    • 4
    • 7
  • S. Shankar
    • 1
    • 5
    • 6
  • T. Teitelbaum
    • 2
    • 4
  1. 1.Carnegie Mellon UniversityPAUSA
  2. 2.Cornell UniversityNYUSA
  3. 3.Fujitsu Labs of AmericaCAUSA
  4. 4.Grammatech, Inc.NYUSA
  5. 5.Hunter College and the Graduate SchoolThe City University of New YorkNYUSA
  6. 6.Verysys Design Automation, Inc.CAUSA
  7. 7.University of WisconsinWIUSA

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