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Practical Application of Formal Verification Techniques on a Frame Mux/Demux Chip from Nortel Semiconductors

  • Y. Xu
  • E. Cerny
  • A. Silburt
  • A. Coady
  • Y. Liu
  • P. Pownall
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1703)

Abstract

We describe the application of model checking using FormalCheck to an industrial RTL design. It was used as a complement to classical simulation on portions of the chip that involved complex interactions and were difficult to verify by simulation. We also identify certain circuit structures that for a certain type of queries lend themselves to manual model reductions which were not detected by the automatic reduction algorithm. These reductions were instrumental in allowing us to complete the formal verification of the design and to detect two design errors that would have been hard to detect by simulation. We also provide a technique to estimate the length of a random simulation needed to detect a particular design error with a given probability; this length can be used as a measure of its difficulty.

Keywords

Model Checker Clock Cycle Model Reduction Formal Verification Design Error 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1999

Authors and Affiliations

  • Y. Xu
    • 1
  • E. Cerny
    • 2
  • A. Silburt
    • 1
  • A. Coady
    • 1
  • Y. Liu
    • 1
  • P. Pownall
    • 1
  1. 1.Nortel SemiconductorsOntarioCanada
  2. 2.Dépt.IROUniversité de MontréalQuébecMontréAlCanada

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