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A Parallel System Architecture Based on Dynamically Configurable Shared Memory Clusters

  • Marek Tudruj
  • Łukasz Masko
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2328)

Abstract

The paper presents a new architectural solution for parallel systems built of shared memory processor clusters. The system is based on dynamically run-time reconfigurable multi-processor clusters; each organized around a local shared memory module placed in a common address space. Each memory module is accessed by a local cluster bus and a common inter-cluster bus. Programs are organized accordingly to their macro dataflow graphs in which tasks and communication are so defined, as to eliminate reloading of data caches during task execution. The behaviour of the proposed system has been evaluated by simulation based on an extended macro dataflow graph representation that includes modelling of data bus arbiters in the system. Program distribution into dynamic processor clusters assumes run—time switching of processors between busses and memory modules. It can reduce contention on data busses. CG algorithm execution in the proposed architecture shows speed—up greater than 4 when 5 busses are applied instead of one.

Keywords

Shared Memory Memory Module Data Cache Shared Memory System Task Node 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Marek Tudruj
    • 1
  • Łukasz Masko
    • 1
  1. 1.Institute of Computer SciencePolish Academy of SciencesWarsawPoland

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