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Overview of IA-64 Explicitly Parallel Instruction Computing Architecture

  • Pawel Gepner
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2328)

Abstract

The intention of this paper is to provide an overview of the IA-64 Explicitly Parallel Instruction Computing (EPIC) architecture. This quick overview of EPIC computer architecture evolution is provided to highlight some of the motivating factors for developing IA-64 architecture as well as showing the most important areas where the architecture has overcome traditional limitations in processor architecture. Before describing the important IA-64 architecture features I will outline the goals and strategy of IA-64 architecture.

Keywords

Memory Latency Intel Corporation Branch Prediction Branch Instruction Streaming SIMD Extension 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Itanium Processor Microarchitecture Reference for Software Optimization, Intel Corporation, August 2000.Google Scholar
  2. 2.
    Intel(R) Itanium(TM) Processor Hardware Developer’s Manual, Intel Corporation, May 2000.Google Scholar
  3. 3.
    Intel(R) Itanium(TM) Architecture Software Developer’s Manual. Vol. 1, rev. 1.1: Application Architecture, Intel Corporation, 1999.Google Scholar
  4. 4.
    Intel(R) Itanium(TM) Architecture Software Developer’s Manual. Vol. 3, rev. 1.1: Instruction Set Reference, Intel Corporation, 1999.Google Scholar
  5. 5.
    Intel(R) Itanium(TM) Architecture Software Developer’s Manual. Vol. 4, rev. 1.1: Itanium Processor Programmer’s Guide, Intel Corporation, 1999.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Pawel Gepner
    • 1
  1. 1.Intel CorporationUSA

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