Abstract
In this paper, the modelling of a Crypto-processor in a FPGA chip based on the Rapid Prototyping of Application Specific Signal Processors (RASSP) design concept is described. By using this concept, the modelling is carried out in a structural manner from the design capture in VHDL code to design synthesis in FPGA prototype. Through this process, the turnaround time of the design cycle is reduced by above 50% compare to normal design cycle. This paper also emphasises on the crypto-processor architecture for space and speed trade-off; design methodology for design insertion and modification; and design automation from virtual prototyping to real hardware. In which above 60% of spatial and 75% of timing reduction is reported in this paper.
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© 1999 Springer-Verlag Berlin Heidelberg
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Choi, W.P., Cheng, L.M. (1999). Modelling the Crypto-Processor from Design to Synthesis. In: Koç, Ç.K., Paar, C. (eds) Cryptographic Hardware and Embedded Systems. CHES 1999. Lecture Notes in Computer Science, vol 1717. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48059-5_4
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DOI: https://doi.org/10.1007/3-540-48059-5_4
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