Abstract
The CryptoBooster is a modular and reconfigurable cryptographic coprocessor that takes full advantage of current high-performance reconfigurable circuits (FPGAs) and their partial reconfigurability. The CryptoBooster works as a coprocessor with a host system in order to accelerate cryptographic operations. A series of cryptographic modules for diffierent encryption algorithms are planned. The first module we implemented is IDEACore, an encryption core for the International Data Encryption Algorithm (IDEA™).
Acknowledgments
The CryptoBooster project is a joint project between the Swiss Federal Institute of Technology in Lausanne and Lightning Instrumentation SA, with funding from the Swiss Federal Office for Education and Technology. The authors are grateful to Moshe Sipper for his careful reading of this work and his helpful comments.
Chapter PDF
Similar content being viewed by others
References
H Bonnenberg, A. Curiger, N. Felber, H. Kaeslin, and X. Lai. VLSI implementation of a new block cipher. In Proceeding of the International Conference on Computer Design: VLSI in Computer and Processors, pages 510–513, Washington, 1991. IEEE, IEEE Computer Society Press.
E. Caspi and N. Weaver. IDEA as a benchmark for recon gurable computing. Technical report, BRASS Research Group, University of Berkeley, December 1996. Report available form http://www.cs.berkeley.edu/projects/brass/projects.html.
A. Curiger, H. Bonnenberg, and H. Kaeslin. Regular VLSI-architectures for multiplication modulo (2n + 1). IEEE Journal of Solid-State Circuits, 26(7):990–994, Jul y 1991.
A. Curiger, H. Bonnenberg, R. Zimmermann, N. Felber, H. Kaeslin, and W. Fichtner. VINCI: VLSI implementation of the new block cipher IDEA. In Proceedings of the IEEE CICC’93, pages 15.5.1–15.5.4, San Diego, CA, May 1993. IEEE.
A. Hiasat. New memoryless modulo (2n + 1) residu multiplierElectronic Letters, 41(3):314–315, January 1992.
ISO. Information technology-security techniques-modes of operation for an n-bit block cipher. International standard ISO/IEC 10116:1997(E), ISO/IEC, 15 April 1997.
X. Lai. On the Design and Security of Block Ciphers. Number 1 in ETH Series in Information Processing. Hartung-Gorre Verlag Konstanz, 1992.
X. Lai and J. Massey. A proposal for a new block encryption standard. In Advances in Cryptology-EUROCRYPT’90, pages 389–404, Berlin, 1990. Springer-Verlag.
X. Lai, J. Massey, and S. Murphy. Markov ciphers and differential cryptanalysis. In Advances in Cryptology-EUROCRYPT’ 91, pages 8–13, Berlin, 1991. Springer-Verlag.
Y. Ma. A simplified architecture for modulo (2n + 1) multiplication. IEEE Transactions on Computers, 47(3):333–337, March 1998.
J. L. Massey and X. Lai. Device for convertig a digital block and the use thereof, 28 Nov 1991. International Patent PCT/CH91/00117.
J. L. Massey and X. Lai. Device for the conversion of a digital block and use of same, 25 May 1993. U.S. Patent #5,214,703.
O. Mencer, M. Morf, and M. J. Flynn. Hardware software tri-design of encryption for mobile communication units. In Proceedings of International Conference on Acoustics, Speech,and Signal Processing, Seattle, Washington, USA, May 1998.
S. Trimberger. Field-Programmable Gate Array Technology. Kluwer Academic Publishers, 1994.
Z. Wang, G. A. Jullien, and W. C. Miller. An efficient tree architecture for modulo (2n+1) multiplication. Journal of VLSI Signal Processing Systems, 14(3):241–248, December 1996.
R. Zimmermann. Efficient VLSI implementation of modulo (2n + 1) addition and multiplication. In Proceedings IEEE Symposium on Computer Arithmetic, Adeleide, Australia, April 1999. IEEE.
R. Zimmermann, A. Curiger, H. Bonnenberg, H. Kaeslin, N. Felber, and W. Fichtner. A 177 Mbit/s VLSI implementation of the international data encryption algorithm. IEEE Journal of Solid-State Circuits, 29(3):303–307, March 1994.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1999 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Mosanya, E., Teuscher, C., Restrepo, H.F., Galley, P., Sanchez, E. (1999). CryptoBooster: A Reconfigurable and Modular Cryptographic Coprocessor. In: Koç, Ç.K., Paar, C. (eds) Cryptographic Hardware and Embedded Systems. CHES 1999. Lecture Notes in Computer Science, vol 1717. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48059-5_21
Download citation
DOI: https://doi.org/10.1007/3-540-48059-5_21
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-66646-2
Online ISBN: 978-3-540-48059-4
eBook Packages: Springer Book Archive