Abstract
This paper investigates the hardware implementation of arithmetical operations (multiplication and inversion) in symmetric and alternating groups, as well as in binary permutation groups (permutation groups of order 2r). Various fast and space-efficient hardware architectures will be presented. High speed is achieved by employing switching networks, which effect multiplication in one clock cycle (full parallelism). Space-efficiency is achieved by choosing, on one hand, proper network architectures and, on the other hand, the proper representation of the group elements. We introduce a non-redundant representation of the elements of binary groups, the so-called compact representation, which allows low-cost realization of arithmetic for binary groups of large degrees such as 128 or even 256. We present highly optimized multiplier architectures operating directly on the compact form of permutations. Finally, we give complexity and performance estimations for the presented architectures
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Alfred V. Aho, John E. Hopcroft, Jeffrey D. Ullmann: The Design and Analysis of Computer Algorithms Addison-Wesley, 1974.
Selim G. Akl: Parallel Sorting Algorithms Academic Press, 1985.
V. E. Beneš, Mathematical Theory of Connecting Networks and Telephone Traffic, Academic Press, 1965
Thomas H. Cormen, Charles E. Leiserson, Ronald L. Rivest: Introduction to Algorithms, MIT Press, 1990.
Tse-yun Feng, A Survey of Interconnection Networks, IEEE Computer, December 1981, pp 12–27.
Alan Gibbons, Wojciech Rytter: Efficient Parallel Algorithms Cambridge University Press, 1988.
A.J. van de Goor: Computer Architecture and Design Addison-Wesley, 1989.
J.P. Hayes: Computer Architecture and Organization McGraw-Hill, 1988.
D. Knuth: The Art of Computer Programming Volume III: Sorting and Searching, Addison-Wesley, 1973.
C. P. Kruskal, M. Snir: ”A Unified Theory of interconnection Network Structure”, Theoretical Computer Science, Volume 48, 1986.
S. S. Magliveras, A cryptosystem from logarithmic signatures of finite groups, In Proceedings of the 29’th Midwest Symposium on Circuits and Systems, Elsevier Publishing Company (1986), pp 972–975.
S. S. Magliveras and N. D. Memon, Algebraic Properties of Cryptosystem PGM, in Journal of Cryptology, 5 (1992), pp 167–183.
T. Horváath, S. Magliveras, Tran van Trung, A Parallel Permutation Multiplier for a PGM Crypto-chip, Advances in Cryptology-CRYPTO’94, Springer-Verlag 1994, pp 108–113.
T. Horváth, Secret-key Cryptosystem TST, Ph.D. thesis, Institut for Experimental Mathematics, University of Essen, Germany, to be published in 1999.
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© 1999 Springer-Verlag Berlin Heidelberg
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Horváth, T. (1999). Arithmetic Design for Permutation Groups. In: Koç, Ç.K., Paar, C. (eds) Cryptographic Hardware and Embedded Systems. CHES 1999. Lecture Notes in Computer Science, vol 1717. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48059-5_11
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DOI: https://doi.org/10.1007/3-540-48059-5_11
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