Abstract
A hardware implementation of an evolutionary algorithm is capable of running much faster than a software implementation. However, the speed advantage of the hardware implementation will disappear for slow fitness evaluation systems. In this paper a Fast Evolutionary Algorithm (FEA) is implemented in hardware to examine the real time advantage of such a system. The timing specifications show that the hardware FEA is approximately 50 times faster than the software FEA. An image compression hardware subsystem is used as the fitness evaluation unit for the hardware FEA to show the benefit of the FEA for time-consuming applications in a hardware environment. The results show that the FEA is faster than the EA and generates better compression ratios.
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References
Holland J., “Adaptation in Natural and Artificial Systems”, MIT Press, Cambridge, MA, 1975.
Back T., “Evolutionary Algorithms in Theory and Practice”, Oxford University Press, New York, 1996.
Salami, M, and Hendtlass T., “A Fitness Evaluation Strategy for Genetic Algorithms”, The Fifteenth International Conference on Industrial and Engineering Application of Artificial Intelligent and Expert Systems (IEA/AIE2002), Cairns, Australia.
Spiessens P., and Manderick B., “A Massively Parallel Genetic Algorithm: Implementation and First Analysis”, Proceedings of the Fourth International Conference on Genetic Algorithms, Morgan Kaufmann, San Mateo CA, pp. 279–285, 1991.
Salami, M., “Genetic Algorithm Processor on Reprogrammable Architectures”, The Proceedings of The Fifth Annual Conference on Evolutionary Programming 1996 (EP96), MIT Press, San Diego, CA, March 1996.
Graham P., and Nelson B., “Genetic Algorithms in software and in Hardware — A Performance analysis of Workstation and Custom Computing Machine Implementation”, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, pp. 341–345, 1997.
Salami, M., Sakanashi, H., Iwata, M., Higuchi, T., “On-line Compression of High Precision Printer Images by Evolvable Hardware”, The Proceedings of The 1998 Data Compression Conference (DCC98), IEEE Computer Society Press, Los Alamitos, CA, USA, 1998.
Weinberger M.J., Seroussi G., and Sapiro G., “LOCO-I: A Low Complexity, Context-Based, Lossless Image Compression Algorithm”, Proceedings of Data Compression Conference (DCC96), Snowbird, Utah, pp. 140–149, April 1996.
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© 2002 Springer-Verlag Berlin Heidelberg
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Salami, M., Hendtlass, T. (2002). A Fast Evolutionary Algorithm for Image Compression in Hardware. In: Hendtlass, T., Ali, M. (eds) Developments in Applied Artificial Intelligence. IEA/AIE 2002. Lecture Notes in Computer Science(), vol 2358. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48035-8_24
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DOI: https://doi.org/10.1007/3-540-48035-8_24
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