Abstract
Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but requires efficient algorithms for the generation of the logic which generates the test vectors applied to the Unit Under Test. This paper addresses the issue of identifying a Cellular Automaton able to generate input patterns to detect stuckat faults inside a Finite State Machine (FSM) circuit. Previous results already proposed a solution based on a Genetic Algorithm which directly identifies a Cellular Automaton able to reach good Fault Coverage of the stuck-at faults. However, such method requires 2-bit cells in the Cellular Automaton, thus resulting in a high area overhead. This paper presents a new solution, with an area occupation limited to 1 bit per cell; the improved results are possible due to the adoption of a new optimization algorithm, the Selfish Gene algorithm. Experimental results are provided, which show that in most of the standard benchmark circuits the Cellular Automaton selected by the Selfish Gene algorithm is able to reach a Fault Coverage higher that what can be obtained with current engineering practice with comparable area occupation.
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6 References
M. Abramovici, M.A. Breuer, A.D. Friedman: “Digital Systems Testing and Testable Design,” Computer Science Press, 1990
These benchmark circuits can be downloaded from the CAD Benchmarking Laborarory at the address http://www.cbl.ncsu.edu/www/CBL_Docs/Bench.html
F. Brglez, D. Bryant, K. Kozminski, “Combinational profiles of sequential benchmark circuits,” Proc. Int. Symp. on Circuits And Systems, 1989, pp. 1929–1934
S. Boubezari, B. Kaminska, “A Deterministic Built-In Self-Test Generator Based on Cellular Automata Structures,” IEEE Trans. on Comp., Vol. 44, No. 6, June 1995, pp. 805–816
K. Cattell, S. Zhang, “Minimal Cost One-Dimensional Linear Hybrid Cellular Automata of Degree Through 500”, JETTA, Journal of Electronic Testing an Test Application, Kluwer, 1995, pp. 255–258
S. Chiusano, F. Corno, P. Prinetto, M. Sonza Reorda, “Cellular Automata for Sequential Test Pattern Generation”, VTS’97: IEEE VLSI Test Symposium, Monterey CA (USA), April 1997, pp. 60–65
F. Corno, N. Gaudenzi, P. Prinetto, M. Sonza Reorda, “On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits”, VTS’98: 16th IEEE VLSI Test Symposium, Monterey, California (USA), April 1998
F. Corno, P. Prinetto, M. Sonza Reorda, “A Genetic Algorithm for Automatic Generation of Test Logic for Digital Circuits”, IEEE International Conference On Tools with Artificial Intelligence, Toulouse (France), November 1996
F. Corno, M. Sonza Reorda, G. Squillero, “The Selfish Gene Algorithm: a New Evolutionary Optimization Strategy”, SAC’98: 13th Annual ACM Symposium on Applied Computing, Atlanta, Georgia (USA), February 1998, pp. 349–355
F. Corno, M. Sonza Reorda, G. Squillero, “A New Evolutionary Algorithm Inspired by the Selfish Gene Theory”, ICEC’98: IEEE International Conference on Evolutionary Computation, May, 1998, pp. 575–580
F. Corno, M. Sonza Reorda, G. Squillero, “Optimizing Deceptive Functions with the SG-Clans Algorithm”, CEC’99: 1999 Congress on Evolutionary Computation, Washington DC (USA), July 1999, pp. 2190–2195
D.E. Goldberg, “Genetic Algorithms in Search, Optimization, and Machine Learning,” Addison-Wesley, 1989
P.D. Hortensius, R.D. McLeod, W. Pries, D.M. Miller, H.C. Card, “Cellular Automata-Based Pseudorandom Number Generators for Built-In Self-Test,” IEEE Trans. on Computer-Aided Design, Vol. 8, No. 8, August 1989, pp. 842–859
JETTA, Journal of Electronic Testing, Theory and Applications, special Issue on Partial Scan Methods, Volume 7, Numbers 1/2, August/October 1995
B. Konemann, J. Mucha, G. Zwiehoff, “Built-In Logic Block Observation Technique,” Proc. IEEE International Test Conference, October 1979, pp. 37–41
A. Krasniewski, S. Pilarski, “Circular Self-Test Path: A low-cost BIST Technique for VLSI circuits,” IEEE Trans. on CAD, Vol. 8, No. 1, January 1989, pp. 46–55
T.M. Niermann, W.-T. Cheng, J.H. Patel, “PROOFS: A Fast, Memory-Efficient Sequential Circuit Fault Simulator,” IEEE Trans. on CAD/ICAS, Vol. 11, No. 2, February 1992, pp. 198–207
J. van Sas, F. Catthoor, H. De Man, “Cellular Automata Based Deterministic Self-Test Strategies for Programmable Data Paths,” IEEE Trans. on CAD, Vol. 13, No. 7, July 1994, pp. 940–949
T. Toffoli, N. Magolus, “Cellular Automata Machines: A New Environment for Modeling,” MIT Press, Cambridge (USA), 1987
S. Wolfram, “Statistical Mechanics of Cellular Automata,” Rev. Mod. Phys. 55, 1983, pp. 601–644
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Corno, F., Reorda, M.S., Squillero, G. (2000). Evolving Cellular Automata for Self-Testing Hardware. In: Miller, J., Thompson, A., Thomson, P., Fogarty, T.C. (eds) Evolvable Systems: From Biology to Hardware. ICES 2000. Lecture Notes in Computer Science, vol 1801. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46406-9_4
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DOI: https://doi.org/10.1007/3-540-46406-9_4
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