Genetic Algorithm-Based Design Methodology for Pattern Recognition Hardware

Abstract

In this paper, we propose a new logic circuit design methodology for pattern recognition chips using the genetic algorithms. In the proposed design methodology, pattern data are transformed into the truth tables and the truth tables are generalized to adapt the unknown pattern data. The genetic algorithm is used to choose the generalization operators. The generalized, or evolved truth tables are then synthesized to logic circuits. Because of this data direct implementation approach, no floating point numerical circuits are required and the intrinsic parallelism in the data is embedded into the circuits. Consequently, high speed recognition systems can be realized with acceptable small circuit size. We have applied this methodology to the face image recognition and the sonar spectrum recognition tasks, and implemented them onto the developed FPGA-based reconfigurable pattern recognition board. The developed system demonstrates high recognition accuracy and much higher processing speed than the conventional approaches.