Challenges and Opportunities for FPGA Platforms

Abstract

Today, FPGA devices contain up to 10 million system gates [1] and within three to four years processing technology will allow us to build 50 million gate devices, i.e. enough logic to build very complex, high performance systems. In addition, these devices operate at internal clock speeds, the equal of most ASIC’s. Although the opportunities for building complex systems with these FPGA platforms are unprecedented, new breakthroughs will be required to solve

• • the design productivity,

• • the scalability of the architectures,

• • the power requirements of embedded computing applications,

• • the ease of use

As device densities keep increasing, a wide variety of hard and soft intellectual property cores are being made available on these platforms. Hardware processors and DSP datapaths are combined with softcores and large embedded memories. Moreover, demand of high performant systems requires the integration of gigabit- per-second serial I/O capability for interconnecting devices, backplanes and systems. These FPGA platforms will have to be accompanied by high level design tools that allow to capture the growing complexity, heterogeneity and flexibility (in time and space) of these components New modeling languages, HW/SW co-design flows, verification techniques and IP- re-use strategies will be required. Research teams from different fields have to join forces to master the problem of such large complexity. [2]

In order to further ride the wave of Moore’s law, advanced FPGA architectures will have to focus on innovative interconnect strategies to further guarantee scalability, flexibility and performance improvements. Whereas today, in case of 0.13 μm process technology, the transfer of a signal over a 1mm wire takes already twice as long as the execution of a 32-bit ALU operation, for a 0.05μm technology the relative interconnect delay will be a factor 9 higher. Moreover, transporting a signal over a 1mm wire, in a 0.05 μm technology will require more than 50 times the energy of a 32 bit ALU operation in the same technology and the off-chip interconnect will consume more than 1000 times the energy of a 32-bit ALU operation. Hence, novel circuit techniques such as overdrive, low-swing signaling as well as new architectures and 3D interconnect/packaging techniques will become essential to mitigate effects of slow wires. [3]