Abstract
Bandwidth efficient communication systems employ highorder modulation schemes like M-ary QAM modulation for reasons of spectral efficiency. Many sophisticated signal processing algorithms are implemented in a QAM demodulator, including adaptive equalization, timing recovery, carrier recovery, automatic gain control and digital down conversion to name a few. This paper examines the FPGA implementation of the adaptive equalizer and carrier recovery loop for a 50 Mbps 16-QAM receiver.
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Dick, C., Harris, F. (2002). FPGA QAM Demodulator Design. In: Glesner, M., Zipf, P., Renovell, M. (eds) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. FPL 2002. Lecture Notes in Computer Science, vol 2438. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46117-5_13
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DOI: https://doi.org/10.1007/3-540-46117-5_13
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