Abstract
This paper deals with the optimized implementation of high performance coherent demodulators in FPGAs for the DVB standard. This work provides design guidelines in order to optimize fixed-point demodulation loops in terms of symbol rate. Several schemes are evaluated such as ROM partitioning techniques and the CORDIC algorithm. We go through the whole design process from simulation to timing analysis for a particular case study. For each architecture we propose the most effficient design for Virtex FPGAs in terms of area and throughput. Finally we will compare them in order to establish the most suitable de-rotator scheme for each transmission bandwidth, and for transmission rates up to 25.8Mbauds.
This work was supported by Generalitat Valenciana under grant number GV00-93- 14. Francisco Cardells-Tormo acknowledges the support of Hewlett-Packard ICD in the preparation of his Ph.D. thesis
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Cardells-Tormo, F., Valls-Coquillat, J., Almenar-Terre, V., Torres-Carot, V. (2002). Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB Standard. In: Glesner, M., Zipf, P., Renovell, M. (eds) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. FPL 2002. Lecture Notes in Computer Science, vol 2438. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46117-5_12
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DOI: https://doi.org/10.1007/3-540-46117-5_12
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